參數(shù)資料
型號(hào)： ADF4350BCPZ-RL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 19/32頁(yè)
文件大?。?/td> 0K
描述： IC SYNTH PLL VCO FN/IN 32LFCSP
產(chǎn)品變化通告： ADF4350, ADF4905/6 N-counter Change 05/Mar/2012
設(shè)計(jì)資源： Broadband Low EVM Direct Conversion Transmitter (CN0134)
Broadband Low EVM Direct Conversion Transmitter Using LO Divide-by-2 Modulator (CN0144)
Using low noise linear drop-out regulators to power wideband PLL & VCO IC's (CN0147)
標(biāo)準(zhǔn)包裝： 5,000
類(lèi)型： 扇出配送，分?jǐn)?shù)-N，整數(shù)-N，時(shí)鐘/頻率合成器（RF）
PLL： 是
輸入： CMOS，TTL
輸出： 時(shí)鐘
電路數(shù)： 1
比率 - 輸入:輸出： 1:3
差分 - 輸入:輸出： 無(wú)/無(wú)
頻率 - 最大： 4.4GHz
除法器/乘法器： 是/是
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤(pán)，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ（5x5）
包裝： 帶卷 (TR)
ADF4350
Rev. A | Page 26 of 32
INTERFACING
The ADF4350 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When LE goes high, the 32 bits that have been clocked
into the appropriate register on each rising edge of CLK are
transferred to the appropriate latch. See Figure 2 for the timing
diagram and Table 5 for the register address table.
ADuC70xx Interface
Figure 35 shows the interface between the ADF4350 and the
ADuC70xx family of analog microcontrollers. The ADuC70xx
family is based on an AMR7 core, although the same interface
can be used with any 8051-based microcontroller. The micro-
controller is set up for SPI master mode with CPHA = 0. To
initiate the operation, the I/O port driving LE is brought low.
Each latch of the ADF4350 needs a 32-bit word. This is accom-
plished by writing four 8-bit bytes from the microcontroller to
the device. When the last byte is written, the LE input should be
brought high to complete the transfer.
On first applying power to the ADF4350, it needs six writes
(one each to R5, R4, R3, R2, R1, R0) for the output to become
active.
I/O port lines on the microcontroller are also used to control
power-down (CE input) and to detect lock (MUXOUT
configured as lock detect and polled by the port input).
When operating in the mode described, the maximum SPI
transfer rate of the ADuC7023 is 20 Mbps. This means that
the maximum rate at which the output frequency can be
changed is 833 kHz. If using a faster SPI clock just make sure
the SPI timing requirements listed in Table 2 are adhered to.
07
32
5-
02
2
ADuC70xx
ADF4350
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
SCLOCK
MOSI
I/O PORTS
Figure 35. ADuC812 to ADF4350 Interface
ADSP-BF527 Interface
Figure 36 shows the interface between the ADF4351 and the
Blackfin ADSP-BF527 digital signal processor (DSP). The
ADF4351 needs a 32-bit serial word for each latch write. The
easiest way to accomplish this using the Blackfin family is to use
the autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 32-bit
word. To program each 32-bit latch, store the four 8-bit bytes,
enable the autobuffered mode, and write to the transmit register
of the DSP. This last operation initiates the autobuffer transfer.
Make sure the clock speeds are within the maximum limits
outlined in Table 2.
07
32
5-
02
3
ADSP-BF527
ADF4350
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
SCK
MOSI
GPIO
I/O FLAGS
Figure 36. ADSP-BF527 to ADF4350 Interface
PCB DESIGN GUIDELINES FOR A CHIP SCALE
PACKAGE
The lands on the chip scale package (CP-32-2) are rectangular.
The PCB pad for these is to be 0.1 mm longer than the package
land length and 0.05 mm wider than the package land width.
The land is to be centered on the pad. This ensures the solder
joint size is maximized. The bottom of the chip scale package
has a central thermal pad.
The thermal pad on the PCB is to be at least as large as the
exposed pad. On the PCB, there is to be a minimum clearance
of 0.25 mm between the thermal pad and the inner edges of the
pad pattern. This ensures that shorting is avoided.
Thermal vias can be used on the PCB thermal pad to improve
the thermal performance of the package. If vias are used, they
are to be incorporated in the thermal pad at 1.2 mm pitch grid.
The via diameter is to be between 0.3 mm and 0.33 mm, and the
via barrel is to be plated with 1 oz. of copper to plug the via.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADF4350BCPZ-RL7 功能描述:IC SYNTH PLL VCO FN/IN 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 頻率合成器 PLL:是 輸入:晶體 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:1 差分 - 輸入:輸出:無(wú)/無(wú) 頻率 - 最大:1GHz 除法器/乘法器:是/無(wú) 電源電壓:4.5 V ~ 5.5 V 工作溫度:-20°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-LSSOP（0.175"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):NJW1504V-TE1-NDNJW1504V-TE1TR
ADF4350BCPZ-U6 制造商:Analog Devices 功能描述:
ADF4350EB1Z 制造商:Analog Devices 功能描述:AD EVAL BOARD - Bulk
ADF4351 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:Wideband Synthesizer
ADF4351BCPZ 功能描述:IC SYNTH PLL VCO 32LFCSP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:2,000 系列:- 類(lèi)型:PLL 時(shí)鐘發(fā)生器 PLL:帶旁路 輸入:LVCMOS，LVPECL 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:2:11 差分 - 輸入:輸出:是/無(wú) 頻率 - 最大:240MHz 除法器/乘法器:是/無(wú) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:32-LQFP 供應(yīng)商設(shè)備封裝:32-TQFP（7x7） 包裝:帶卷 (TR)
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