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參數(shù)資料
| 型號(hào)： | ADF4206BRUZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 3/24頁 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 16TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 時(shí)鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS |
| 輸出： | 時(shí)鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 3:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 550MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | ADF4206BRUZ-RLDKR |
ADF4206/ADF4208
Rev. A | Page 11 of 24
CIRCUIT DESCRIPTION
REFERENCE INPUT SECTION
The reference input stage is shown in Figure 22. SW1 and SW2
are normally closed switches. SW3 is normally open. When
power-down is initiated, SW3 is closed and SW1 and SW2 are
opened. Typical recommended external components are shown
in Figure 22.
30pF
OSCIN
OSCOUT
TO R
COUNTER
BUFFER
POWER-DOWN
CONTROL
SW1
NC
SW2
100k
SW3
NO
18k
30pF
0
103
6-
022
Figure 22. Reference Input Stage
RF INPUT STAGE
The RF input stage is shown in Figure 23. It is followed by a
2-stage limiting amplifier to generate the CML clock levels
needed for the prescaler.
RFINA
AVDD
BIAS
GENERATOR
1.6V
2k
AGND
2k
RFINB
01
036
-023
Figure 23. RF Input Stage
PRESCALER
The dual modulus prescaler (P/P + 1), along with the A and
B counters, enables the large division ratio, N, to be realized
(N = BP + A). This prescaler, operating at CML levels, takes
the clock from the RF input stage and divides it down to a
manageable frequency for the CMOS A and B counters. It is
based on a synchronous 4/5 core.
The prescaler is selectable. Both RF1 and RF2 can be set to
either 32/33 or 64/65. DB20 of the AB counter latch selects the
A AND B COUNTERS
The A and B CMOS counters combine with the dual modulus
prescaler to allow a wide ranging division ratio in the PLL
feedback counter. The devices are guaranteed to work when the
prescaler output is 200 MHz or less.
PULSE SWALLOW FUNCTION
The A and B counters, in conjunction with the dual modulus
prescaler, make it possible to generate output frequencies that
are spaced only by the reference frequency divided by R. The
equation for the VCO frequency is
fVCO = [(P × B) + A] × fREFIN/R
where:
fVCO is the output frequency of the external voltage controlled
oscillator (VCO).
P is the preset modulus of the dual modulus prescaler
(32/33, 64/65).
B is the preset divide ratio of the binary 11-bit counter
(2 to 2047).
A is the preset divide ratio of the binary 6-bit A counter
(0 to 63).
fREFIN is the output frequency of the external reference frequency
oscillator.
R is the preset divide ratio of the binary 14-bit programmable
reference counter (1 to 16,383).
R COUNTER
The 14-bit R counter allows the input reference frequency to be
divided down to produce the reference clock to the phase
frequency detector (PFD). Division ratios from 1 to 16,383 are
allowed.
PRESCALER
P/P + 1
MODULUS
CONTROL
FROM RF
INPUT STAGE
LOAD
N = BP + A
N DIVIDER
LOAD
TO PFD
11-BIT B
COUNTER
6-BIT A
COUNTER
01
03
6-
0
24
Figure 24. A and B Counters
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