VDD1 = V
參數(shù)資料
型號: ADF4206BRUZ-RL
廠商: Analog Devices Inc
文件頁數(shù): 20/24頁
文件大?。?/td> 0K
描述: IC PLL FREQ SYNTHESIZER 16TSSOP
產(chǎn)品變化通告: Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率合成器,RF
PLL:
輸入: CMOS
輸出: 時(shí)鐘
電路數(shù): 1
比率 - 輸入:輸出: 3:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 550MHz
除法器/乘法器: 無/無
電源電壓: 2.7 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: ADF4206BRUZ-RLDKR
ADF4206/ADF4208
Rev. A | Page 5 of 24
TIMING SPECIFICATIONS
VDD1 = VDD2 = 3 V ± 10%, 5 V ± 10%; VDD1, VDD2 ≤ VP1, VP2 ≤ 6.0 V; AGNDRF1 = DGNDRF1 = AGNDRF2 = DGNDRF2 = 0 V;
TA = TMIN to TMAX, unless otherwise noted; dBm referred to 50 Ω.
Table 2.
Parameter1
Limit at TMIN to TMAX (B Version)
Unit
Test Conditions/Comments
t1
10
ns min
DATA to CLK setup time
t2
10
ns min
DATA to CLK hold time
t3
25
ns min
CLK high duration
t4
25
ns min
CLK low duration
t5
10
ns min
CLK to LE setup time
t6
20
ns min
LE pulse width
1 Guaranteed by design but not production tested.
TIMING DIAGRAM
DB0 (LSB)
(CONTROL BIT C1)
CLK
DB21 (MSB)
DB20
DB2
DATA
LE
t3
t4
t2
t5
t1
t6
DB1
(CONTROL BIT C2)
01
03
6-
0
02
Figure 2. Timing Diagram
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