參數(shù)資料
型號: ADF4158WCCPZ-RL7
廠商: Analog Devices Inc
文件頁數(shù): 25/36頁
文件大?。?/td> 0K
描述: IC FRAC-N FREQ SYNTH 24LFCSP
標準包裝: 1,500
類型: 分數(shù) N 合成器(RF)
PLL:
輸入: CMOS,TTL
輸出: 時鐘
電路數(shù): 1
比率 - 輸入:輸出: 2:1
差分 - 輸入:輸出: 是/無
頻率 - 最大: 6.1GHz
除法器/乘法器: 是/是
電源電壓: 2.7 V ~ 3.3 V
工作溫度: -40°C ~ 125°C
安裝類型: 表面貼裝
封裝/外殼: 24-WFQFN 裸露焊盤,CSP
供應商設備封裝: 24-LFCSP-WQ(4x4)
包裝: 帶卷 (TR)
Data Sheet
ADF4158
Rev. G | Page 31 of 36
F
RE
Q
UE
NC
Y
L
O
G
IC
L
EVEL
TIME
TIME OF INTERRUPT
FREQUENCY AT WHICH INTERRUPT TOOK PLACE
INTERRUPT SIGNAL
LOGIC HIGH
LOGIC LOW
1. SWEEP CONTINUES MODE
2. SWEEP STOPS MODE
12
08
728
-03
0
Figure 43. Interrupt and Frequency Readback
Note that DB[22:21] in Register R4 should be set to 0b10 and
DB[30:27] in Register R0 (MUXOUT control) should be
set to 15 (1111).
The mechanism of how single bits are read back is shown in
For continuous frequency readback the following sequence
should be used:
Register 0 write
LE high
Pulse on TXDATA
Frequency readback (as described at the beginning of the
Pulse on TXDATA
Register R4 write
Frequency readback (as described at the beginning of the
Pulse on TXDATA
The sequence is also shown in Figure 45.
08
728
-10
1
MUXOUT
CLK
LE
TXDATA
DATA CLOCKED OUT ON POSITIVE EDGE OF CLK AND READ ON NEGATIVE EDGE
OF CLK READBACK WORD (37 BITS)
0 0001 1100 1111 0110 0010 0011 1010 0111 1000 (HEX 01CF623A78)
LSB
MSB
12-BIT INTEGER WORD
0000 1110 0111
0x0E7
231
25-BIT FRAC WORD
1 0110 0010 0011 1010 0111 1000
0x1623A78
23214712
RF =
fPFD × (231 + 23214712 ÷ 225) = 5.7922963GHz
Figure 44. Reading Back Single Bits to Determine the Output Frequency at the Moment of Interrupt
CLK
MUXOUT
LE
TXDATA
DATA
R0 WRITE
R4 WRITE
FREQUENCY
READBACK
FREQUENCY
READBACK
FREQUENCY
READBACK
37 CLK
PULSES
37 CLK
PULSES
37 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
32 CLK
PULSES
0
8728-
1
44
Figure 45. Continuous Frequency Readback
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