- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄9225 > ADF4112BRUZ (Analog Devices Inc)IC SYNTH PLL RF 3.0GHZ 16-TSSOP PDF資料下載
參數(shù)資料
| 型號： | ADF4112BRUZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 26/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SYNTH PLL RF 3.0GHZ 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 96 |
| 類型： | 時鐘/頻率合成器，RF |
| PLL： | 是 |
| 輸入： | CMOS，TTL |
| 輸出： | 時鐘 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:1 |
| 差分 - 輸入:輸出： | 是/無 |
| 頻率 - 最大： | 3GHz |
| 除法器/乘法器： | 是/無 |
| 電源電壓： | 2.7 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 551 (CN2011-ZH PDF) |
| 配用： | EVAL-ADF4112EBZ1-ND - BOARD EVAL FOR ADF4112 EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁當(dāng)前第26頁第27頁第28頁
Data Sheet
ADF4110/ADF4111/ADF4112/ADF4113
Rev. F | Page 7 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
DVDD
MUXOUT
LE
VP
DATA
CLK
CE
DGND
RSET
CP
CPGND
AGND
RFINB
RFINA
AVDD
REFIN
TOP VIEW
(Not to Scale)
ADF4110
ADF4111
ADF4112
ADF4113
03496-0-003
03496-
0-
004
NOTES
1. THE EXPOSED PADDLE SHOULD BE CONNECTED TO AGND.
14
13
12
1
3
4
LE
15 MUXOUT
DATA
CLK
11 CE
CPGND
AGND
2
AGND
RFINB
5
RFINA
7
AV
DD
6
AV
DD
8
RE
F
IN
9
DG
ND
10
DG
ND
19
R
SET
20
CP
18
V
P
17
DV
DD
16
DV
DD
ADF4110
ADF4111
ADF4112
ADF4113
TOP VIEW
(Not to Scale)
Figure 3. TSSOP Pin Configuration
Figure 4. LFCSP Pin Configuration
Table 4. Pin Function Descriptions
TSSOP
Pin No.
LFCSP
Pin No.
Mnemonic
Function
1
19
RSET
Connecting a resistor between this pin and CPGND sets the maximum charge pump output current.
The nominal voltage potential at the RSET pin is 0.56 V. The relationship between ICP and RSET is
SET
max
CP
R
I
5
.
23
=
So, with RSET = 4.7 k, ICPmax = 5 mA.
2
20
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn
drives the external VCO.
3
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
4
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
5
4
RFINB
Complementary Input to the RF Prescaler. This point should be decoupled to the ground plane with
a small bypass capacitor, typically 100 pF. See Figure 29.
6
5
RFINA
Input to the RF Prescaler. This small-signal input is ac-coupled from the VCO.
7
6, 7
AVDD
Analog Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the analog ground
plane should be placed as close as possible to this pin. AVDD must be the same value as DVDD.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2, and an equivalent input
resistance of 100 k. See Figure 28. This input can be driven from a TTL or CMOS crystal oscillator, or
can be ac-coupled.
9
9, 10
DGND
Digital Ground.
10
11
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into
three-state mode. Taking the pin high powers up the device depending on the status of the power-
down Bit F2.
11
12
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance CMOS
input.
12
13
DATA
Serial Data Input. The serial data is loaded MSB first with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13
14
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches; the latch is selected using the control bits.
14
15
MUXOUT
This multiplexer output allows either the lock detect, the scaled RF, or the scaled reference
frequency to be accessed externally.
15
16, 17
DVDD
Digital Power Supply. This may range from 2.7 V to 5.5 V. Decoupling capacitors to the digital ground
plane should be placed as close as possible to this pin. DVDD must be the same value as AVDD.
16
18
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V,
VP can be set to 6 V and used to drive a VCO with a tuning range of up to 6 V. 1
EPAD
Exposed Pad (LFCSP Only). The exposed paddle should be connected to AGND.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-BTX-MW-B1 | CONVERTER MOD DC/DC 5.2V 100W |
| ADF4113BCPZ | IC PLL FREQ SYNTHESIZER 20-LFCSP |
| X9429WS16Z-2.7 | IC XDCP SGL 64-TAP 10K 16-SOIC |
| VI-BTX-MV | CONVERTER MOD DC/DC 5.2V 150W |
| VE-B4P-IU-B1 | CONVERTER MOD DC/DC 13.8V 200W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4112BRUZ | 制造商:Analog Devices 功能描述:PLL/FREQUENCY SYNTHESIZER IC |
| ADF4112BRUZ-REEL | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4112BRUZ-REEL7 | 功能描述:IC PLL RF FREQ SYNTHESZR 16TSSOP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:Precision Edge® 類型:時鐘/頻率合成器 PLL:無 輸入:CML，PECL 輸出:CML 電路數(shù):1 比率 - 輸入:輸出:2:1 差分 - 輸入:輸出:是/是 頻率 - 最大:10.7GHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-VFQFN 裸露焊盤，16-MLF? 供應(yīng)商設(shè)備封裝:16-MLF?（3x3） 包裝:帶卷 (TR) 其它名稱:SY58052UMGTRSY58052UMGTR-ND |
| ADF4113 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| ADF4113BCHIPS | 制造商:AD 制造商全稱:Analog Devices 功能描述:RF PLL Frequency Synthesizers |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。