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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Phase Detector/Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 400 MHz, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 18/24頁 |
| 文件大?。?/td> | 336K |
| 代理商： | ADF4002BRUZ-RL7 |
ADF4002
PFD
As the ADF4002 permits both R and N counters to be
programmed to 1, the part can effectively be used as a stand
alone PFD and charge pump. This is particularly useful in either
a clock cleaning application or a high performance LO. Addi-
tionally, the very low normalized phase noise floor (222 dBc/Hz)
enables very low in-band phase noise levels. It is possible to
operate the PFD up to a maximum frequency of 200 MHz.
Rev. 0 | Page 18 of 24
In Figure 22, the reference frequency equals the PFD, therefore,
R = 1. The charge pump output integrates into a stable control
voltage for the VCXO, and the output from the VCXO is
divided down to the desired PFD frequency using an external
divider.
0
8
2
16
15
7
6
5
9
4
3
1
REF
IN
REF
IN
R
SET
RF
IN
A
RF
IN
B
A
D
D
D
C
A
D
V
DD
V
P
V
P
C
ADF4002
DECOUPLING CAPACITORS AND
Figure 22. ADF4002 as a PFD
100pF
100pF
51
10k
LOOP
GND
OR
VCXO
V
CC
GND
EXTERNAL PRESCALER
18
18
18
100pF
100pF
RF
OUT
V
CC
V
CC
INTERFACING
The ADF4002 has a simple SPI-compatible serial interface for
writing to the device. CLK, DATA, and LE control the data
transfer. When the latch enable (Pin LE) goes high, the 24 bits
that have been clocked into the input register on each rising
edge of CLK are transferred to the appropriate latch. For more
information, see Figure 2 for the timing diagram and Table 6 for
the latch truth table.
The maximum allowable serial clock rate is 20 MHz. This
means that the maximum update rate possible for the device is
833 kHz, or one update every 1.2 μs. This is certainly more than
adequate for systems that have typical lock times in hundreds of
microseconds.
ADuC812 Interface
Figure 23 shows the interface between the ADF4002 and the
ADuC812
MicroConverter. Since the
ADuC812
is based on an
8051 core, this interface can be used with any 8051-based
microcontroller. The MicroConverter is set up for SPI master
mode with CPHA = 0. To initiate the operation, the I/O port
driving LE is brought low. Each latch of the ADF4002 needs a
24-bit word. This is accomplished by writing three, 8-bit bytes
from the MicroConverter to the device. When the third byte
has been written, bring the LE input high to complete the
transfer.
On first applying power to the ADF4002, it needs four writes
(one each to the initialization latch, function latch, R counter
latch, and N counter latch) for the output to become active.
I/O port lines on the
ADuC812
are also used to control power-
down (CE input) and to detect lock (MUXOUT configured as
lock detect and polled by the port input).
When operating in the SPI master mode, the maximum
SCLOCK rate of the
ADuC812
is 4 MHz. This means that the
maximum rate at which the output frequency can be changed is
166 kHz.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
MOSI
SCLOCK
I/O PORTS
ADuC812
ADF4002
0
Figure 23. ADuC812 to ADF4002 Interface
ADSP2181 Interface
Figure 24 shows the interface between the ADF4002 and the
ADSP21xx digital signal processor. The ADF4002 needs a
24-bit serial word for each latch write. The easiest way to
accomplish this using the ADSP21xx family is to use the
autobuffered transmit mode of operation with alternate
framing. This provides a means for transmitting an entire block
of serial data before an interrupt is generated. Set up the word
length for 8 bits and use three memory locations for each 24-bit
word. To program each 24-bit latch, store the three 8-bit bytes,
enable the autobuffered mode, and then write to the transmit
register of the DSP. This last operation initiates the autobuffer
transfer.
CLK
DATA
LE
CE
MUXOUT
(LOCK DETECT)
ADSP21xx
ADF4002
DT
SCLK
I/O FLAGS
TFS
0
Figure 24. ADSP-21xx to ADF4002 Interface
PCB DESIGN GUIDELINES FOR CHIP SCALE
PACKAGE
The lands on the lead frame chip scale package (CP-20-1) are
rectangular. The printed circuit board pad for these should be
0.1 mm longer than the package land length and 0.05 mm wider
than the package land width. The land should be centered on
the pad. This ensures that the solder joint size is maximized.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4002SRU-EP | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Rail/Tube 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRU-EP-RL7 | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Tape and Reel 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRUZ-EP | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:96 |
| ADF4002SRUZ-EP-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1,000 |
| ADF4007 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Frequency Divider/PLL Synthesizer |
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