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參數(shù)資料
| 型號： | ADF4002BRUZ-RL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | Phase Detector/Frequency Synthesizer |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 400 MHz, PDSO16 |
| 封裝： | ROHS COMPLIANT, MO-153AB, TSSOP-16 |
| 文件頁數(shù)： | 17/24頁 |
| 文件大?。?/td> | 336K |
| 代理商： | ADF4002BRUZ-RL7 |
ADF4002
APPLICATIONS
VERY LOW JITTER ENCODE CLOCK FOR HIGH
SPEED CONVERTERS
Figure 21 shows the ADF4002 with a VCXO to provide the
encode clock for a high speed analog-to-digital converter (ADC).
Rev. 0 | Page 17 of 24
The converter used in this application is an
AD9215-80
, a 12-bit
converter that accepts up to an 80 MHz encode clock. To realize
a stable low jitter clock, use a 77.76 MHz, narrow band VCXO.
This example assumes a 19.44 MHz reference clock.
To minimize the phase noise contribution of the ADF4002, the
smallest multiplication factor of 4 is used. Thus, the R divider is
programmed to 1, and the N divider is programmed to 4.
The charge pump output of the ADF4002 (Pin 2) drives the
loop filter. The loop filter bandwidth is optimized for the best
possible rms jitter, a key factor in the signal-to-noise ratio
(SNR) of the ADC. Too narrow a bandwidth allows the VCXO
noise to dominate at small offsets from the carrier frequency.
Too wide a bandwidth allows the ADF4002 noise to dominate at
offsets where the VCXO noise is lower than the ADF4002 noise.
Thus, the intersection of the VCXO noise and the ADF4002 in-
band noise is chosen as the optimum loop filter bandwidth.
The design of the loop filter uses the ADIsimPLL (Version 3.0)
and is available as a free download from
www.analog.com/pll
.
The rms jitter is measured at <1.2 ps. This level is lower than
the maximum allowable 6 ps rms required to ensure the
theoretical SNR performance of 59 dB for this converter.
The setup shown in Figure 21 using the ADF4002, AD9215, and
HSC-ADC-EVALA-SC, allows the user to quickly and
effectively determine the suitability of the converter and encode
clock. The SPI interface is used to control the ADF4002, and
the USB interface helps control the operation of the AD9215-
80. The controller board sends back FFT information to the PC
that, if using an ADC analyzer, provides all conversion results
from the ADC.
VCXO: 77.76MHz
HC-ADC-EVALA-SC
PC
U
TCXO:
19.44MHz
ENCODE
CLOCK
A
IN
ADF4002
N = 4
PD
R = 1
SPI
AGILENT:
500kHz, 1.8V p-p
0
AD9215-80
Figure 21. ADF4002 as Encode Clock
相關(guān)PDF資料 |
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| ADF4156 | 6 GHz Fractional-N Frequency Synthesizer |
| ADF4156BCPZ | 6 GHz Fractional-N Frequency Synthesizer |
| ADF4156BCPZ-RL | 6 GHz Fractional-N Frequency Synthesizer |
| ADF4156BCPZ-RL7 | 6 GHz Fractional-N Frequency Synthesizer |
| ADF4156BRUZ | 6 GHz Fractional-N Frequency Synthesizer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADF4002SRU-EP | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Rail/Tube 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRU-EP-RL7 | 制造商:Analog Devices 功能描述:Phase Detector/Frequency Synthesizer 16-Pin TSSOP T/R 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE 制造商:Analog Devices 功能描述:LOW FREQUENCY PLL CLOCK SOURCE - Tape and Reel 制造商:Analog Devices 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:Analog Devices Inc. 功能描述:Phase Locked Loops - PLL Low Frequency PLL Clock Source |
| ADF4002SRUZ-EP | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:96 |
| ADF4002SRUZ-EP-RL7 | 功能描述:IC PLL FREQUENCY SYNTH 16TSSOP 制造商:analog devices inc. 系列:* 零件狀態(tài):在售 標(biāo)準(zhǔn)包裝:1,000 |
| ADF4007 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Frequency Divider/PLL Synthesizer |
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