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參數(shù)資料
| 型號： | ADE7759ARS |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 8-Channel 14-Bit Single-Supply Voltage-Output DAC; Package: LQFP (10x10mm); No of Pins: 52; Temperature Range: Industrial |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO20 |
| 封裝： | SSOP-20 |
| 文件頁數(shù)： | 31/32頁 |
| 文件大小： | 530K |
| 代理商： | ADE7759ARS |
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REV. 0
ADE7759
–31–
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
ADDR: 06H
DISHPF
(DISABLE HPF1 IN CHANNEL 1)
DISLPF2
(DISABLE LPF2 AFTER MULTIPLIER)
DISCF
(DISABLE FREQUENCY OUTPUT CF)
DISSAG
(DISABLE
SAG
OUTPUT)
ASUSPEND
(SUSPEND CH1 AND CH2 ADC
’
s)
STEMP
(START TEMPERATURE SENSING)
SWRST
(SOFTWARE CHIP RESET)
CYCMODE
(LINE CYCLE ENERGY ACCUMULATION MODE)
TEST1
(TEST MODE SELECTION SHOULD BE SET TO 0)
WAVSEL
(WAVEFORM SELECTION FOR SAMPLE MODE)
00 = LPF2
01 = CH1 + CH2 (40-BIT WAVEFORM SAMPLES)
10 = CH1
11 = CH2
DTRT
(WAVEFORM SAMPLES OUTPUT DATA RATE)
00 = 27.9kSPS (CLKIN/128)
01 = 14.4kSPS (CLKIN/256)
10 = 7.2kSPS (CLKIN/512)
11 = 3.6kSPS (CLKIN/1024)
SWAP
(SWAP CH1 AND CH2 ADCs)
DISCH2
(SHORT THE ANALOG INPUTS ON CHANNEL 2)
DISCH1
(SHORT THE ANALOG INPUTS ON CHANNEL 1)
NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS
Figure 48. Mode Register
Interrupt Status Register (04H)/Reset Interrupt Status Register (05H)
The Status register is used by the MCU to determine the source of an interrupt request (
IRQ
). When an interrupt event occurs in the
ADE7759, the corresponding flag in the Interrupt Status register is set logic high. If the enable bit for this flag is Logic 1 in the Inter-
rupt Enable register, the
IRQ
logic output goes active low. When the MCU services the interrupt, it must first carry out a read from
the Interrupt Status register to determine the source of the interrupt.
Table VII. Interrupt Status Register, Reset Interrupt Status Register, and Interrupt Enable Register
Bit
Location
Interrupt
Flag
Description
0
1
2
AEHF
SAG
CYCEND
Indicates that an interrupt was caused by the 0 to 1 transition of the MSB of the Active Energy register.
Indicates that an interrupt was caused by a SAG on the line voltage or no zero crossings were detected.
Indicates the end of energy accumulation over an integer number of half line cycles as defined by
the content of the LINECYC register—see Line Cycle Energy Accumulation Mode section
.
Indicates that new data is present in the Waveform register.
This status bit reflects the status of the ZX logic ouput—see Zero Crossing Detection section.
Indicates that a temperature conversion result is available in the Temperature register.
Indicates the end of a reset (for both software or hardware reset). The corresponding enable bit has
no function in the Interrupt Enable register, i.e., this status bit is set at the end of a reset, but it
cannot be enabled to cause an interrupt.
Indicates that the Active Energy register has overflowed.
3
4
5
6
WSMP
ZX
TEMP
RESET
7
AEOF
0
1
0
0
0
0
0
0
7
6
5
4
3
2
1
0
ADDR: 04H/RESET: 05H
AEHF
(ACTIVE ENERGY REGISTER HALF FULL)
SAG
(LINE VOLTAGE SAG DETECT)
CYCEND
(LINE CYCLE ENERGY ACCUMULATION END)
WSMP
(WAVEFORM SAMPLING)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
TEMP
(TEMPERATURE REGISTER READY)
ZX
(ZERO CROSSING DETECTED)
RESET
(END OF A HARDWARE OR SOFTWARE RESET)
NOTE: REGISTER CONTENTS SHOW POWER ON DEFAULTS
Figure 49. Interrupt Status Register
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