參數(shù)資料
型號(hào)： ADE7758ARWRL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： MS-013-AD, SOIC-24
文件頁(yè)數(shù)： 40/68頁(yè)
文件大?。?/td> 1584K
代理商： ADE7758ARWRL
ADE7758
Rev. A | Page 40 of 68
0
VOLTAGE RMS SIGNAL
0x174BAC
60Hz
0x0
0x17F263
50Hz
0x0
CURRENT RMS SIGNAL
0x1C82B
0x00
MULTIPLIER
IRMS
VRMS
VAG[11:0]
VADIV[7:0]
+
+
LPF2
%
VARHR[15:0]
15
0
40
0
APPARENT POWER IS
ACCUMULATED (INTEGRATED) IN
THE VA-HR ACCUMULATION REGISTERS
Figure 75. ADE7758 Apparent Energy Accumulation
Table 10. Inputs to VA-Hr Accumulation Registers
CONSEL[1, 0]
00
AVAHR
VARMS × IARMS
BVAHR
VBRMS × IBRMS
VARMS
+
2
VBRMS × IBRMS
Reserved
CVAHR
VCRMS × ICRMS
01
VARMS × IARMS
IBRMS
VCRMS
×
VCRMS × ICRMS
10
11
Note:
VARMS/VBRMS/VCRMS
are the rms voltage waveform, and
IARMS/IBRMS/ICRMS
are the rms values of the current waveform.
VARMS × IARMS
Reserved
VCRMS × ICRMS
Reserved
Energy Accumulation Mode
The apparent power accumulated in each VA-hr accumulation
register (AVAHR, BVAHR, or CVAHR) depends on the con-
figuration of the CONSEL bits in the COMPMODE register
(Bit 0 and Bit 1). The different configurations are described in
Table 10.
The contents of the VA-hr accumulation registers are affected
by both the gain registers for the current (IGAIN) and rms
voltage gain (VRMSGAIN), as well as the VAGAIN register of
the corresponding phase. IGAIN should not be used when
using CONSEL Mode 0, COMPMODE[0:1].
Apparent Power Frequency Output
Pin 17 (VARCF) of the ADE7758 can provide frequency output
for the total apparent power. By setting the VACF bit (Bit 7) of
the WAVMODE register, this pin provides an output frequency
that is directly proportional to the total apparent power.
A digital-to-frequency converter (DFC) is used to generate the
pulse output from the total apparent power. The TERMSEL bits
(Bit 2 to Bit 4) of the COMPMODE register can be used to
select which phases to include in the total power calculation.
Setting Bit 2, Bit 3, and Bit 4 includes the input to the AVAHR,
BVAHR, and CVAHR registers in the total active power
calculation. A pair of frequency divider registers, namely
VARCFDEN and VARCFNUM, can be used to scale the output
frequency of this pin. Note that either VAR or apparent power
can be selected at one time for this frequency output (see the
Reactive Power Frequency Output section).
Line Cycle Apparent Energy Accumulation Mode
The line cycle apparent energy accumulation mode is activated
by setting the LVA bit (Bit 2) in the LCYCMODE register. The
total apparent energy accumulated over an integer number of
zero crossings is written to the VA-hr accumulation registers
after the LINECYC number of zero crossings has been detected.
The operation of this mode is similar to watt-hr accumulation
(see the Line Cycle Active Energy Accumulation Mode section).
When using the line cycle accumulation mode, the RSTREAD
bit (Bit 6) of the LCYCMODE register should be set to Logic 0.
Note that this mode is especially useful when the user chooses
to perform the apparent energy calculation using the vectorial
method. By setting LWATT and LVAR bits (Bit 0 and Bit 1) of
the LCYCMODE register, the active and reactive energies are
accumulated over the same period of time. Therefore, the MCU
can perform the squaring of the two terms and then take the
square root of their sum to determine the apparent energy over
the same period of time.
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