參數(shù)資料
型號(hào)： ADE7758ARWRL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： MS-013-AD, SOIC-24
文件頁(yè)數(shù)： 37/68頁(yè)
文件大小： 1584K
代理商： ADE7758ARWRL
ADE7758
Rev. A | Page 37 of 68
0
VARG[11:0]
VARDIV[7:0]
90
°
PHASE
SHIFTING FILTER
π
2
MULTIPLIER
I
V
HPF
CURRENT SIGNAL–i(t)
0x2851EC
0x00
0xD7AE14
VOLTAGE SIGNAL–v(t)
0x2852
0x00
0xD7AE
+
+
+
+
LPF2
%
SIGN
2
6
2
0
2
–1
2
–2
2
–3
2
–4
VAROS[11:0]
VARHR[15:0]
15
0
40
0
TOTAL REACTIVE POWER IS
ACCUMULATED (INTEGRATED) IN
THE VAR-HR ACCUMULATION REGISTERS
Figure 72. ADE7758 Reactive Energy Accumulation
Energy Accumulation Mode
The reactive power accumulated in each VAR-hr accumulation
register (AVARHR, BVARHR, or CVARHR) depends on the
configuration of the CONSEL bits in the COMPMODE register
(Bit 0 and Bit 1). The different configurations are described in
Table 9.
Table 9. Inputs to VAR-Hr Accumulation Registers
CONSEL[1, 0]
AVARHR
00
VA × IA’
01
VA(IA’ – IB’)
10
VA(IA’ – IB’)
11
Reserved
When overflow occurs, the VAR-hr accumulation registers
content can rollover to full-scale negative (0x8000) and continue
increasing in value when the reactive power is positive. Con-
versely, if the reactive power is negative the VAR-hr accumulation
registers content can roll over to full-scale positive (0x7FFF)
and continue decreasing in value.
By setting the REHF bit (Bit 1) of the mask register, the
ADE7758 can be configured to issue an interrupt (IRQ) when
Bit 14 of any one of the three VAR-hr accumulation registers
has changed, indicating that the accumulation register is half
full (positive or negative).
BVARHR
VB × IB
0
0
Reserved
CVARHR
VC × IC’
VC (IC’ – IB’)
VC × IC’
Reserved
Note that IA’/IB’/IC’ are the current phase shifted current waveform.
Setting the RSTREAD bit (Bit 6) of the LCYMODE register
enables a read-with-reset for the VAR-hr accumulation
registers, i.e., the registers are reset to 0 after a read operation.
Integration Time Under Steady Load
The discrete time sample period (T) for the accumulation
register is 0.4 μs (4/CLKIN). With full-scale sinusoidal signals
on the analog inputs, and a 90° phase difference between the
voltage and the current signal (the largest possible reactive
power), and the VAR gain registers set to 0x000, the average
word value from each LPF2 is 0xCCCCD. The maximum value
that can be stored in the reactive energy register before it
overflows is 2
15
1 or 0x7FFF. As the average word value is first
added to the internal register, which can store 2
40
1 or 0xFF,
FFFF, FFFF before it overflows, the integration time under these
conditions with VARDIV = 0 is calculated as
The contents of the VAR-hr accumulation registers are affected
by both the current gain register (IGAIN) and the VAR gain
register of the corresponding phase.
Reactive Power Frequency Output
Pin 17 (VARCF) of the ADE7758 provides frequency output for
the total reactive power. Similar to APCF, this pin provides an
output frequency that is directly proportional to the total reactive
power. The pulse width of VARPCF is 64 × CLKIN if VARCFNUM
and VARCFDEN are both equal. If VARCFDEN is greater than
VARCFNUM, the pulse width depends on VARCFDEN. The
pulse width in this case is T × (VARCFDEN/2), where T is the
period of the VARCF pulse and VARCFDEN/2 is rounded to
the nearest whole number. An exception to this is when the
period is greater than 180 ms. In this case, the pulse width is
fixed at 90 ms.
second
0.5243
μs
0.4
0xCCCCD
FFFF
FFFF,
0xFF,
=
×
=
Time
When VARDIV is set to a value different from 0, the time
before overflow are scaled accordingly as shown in Equation 21.
(
)
0
VARDIV
Time
Time
=
=
VARDIV
×
(21)
A digital-to-frequency converter (DFC) is used to generate the
VARCF pulse output from the total reactive power. The TERMSEL
bits (Bit 2 to Bit 4) of the COMPMODE register can be used to
select which phases to be included in the total reactive power
calculation. Setting Bit 2, Bit 3, and Bit 4 includes the input to
the AVARHR, BVARHR, and CVARHR registers in the total
active power calculation. The total reactive power is signed
addition. However, setting the SAVAR bit (Bit 6) in the
COMPMODE register enables absolute value calculation.
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