ADE7753
–37–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
R E V ISION H IST OR Y
T he main reason for revising the datasheet from version Pr.D
to Pr.F is to correct some of the mistakes contained in the
Pr.D and Pr.E version. In addition, changes were made to the
silicon to fix bugs noted in the Errata list and to modify the
product definition. T he list below highlights the important
changes from Pr.D to Pr.F. Note that all page numbers are
referring to that of Pr.F.
Page 4
Read timing t
9
is determined to be 3.1us.
Page 12
T he SAGCY C register value represents full-line cycles and
not half-line cycles. T he line voltage SAG detection section
text was changed to reflect this design update. Figure 13
shows 3 line cycles, 3h in the SAGCY C register, changed
from 6 half line cycles, 6h in the SAGCY C register. T he
section explaining Figure 13 has also changed accordingly.
Page 13
Peak L evel record section was changed to show that the
quantity stored in VPEAK register is 2 times the absolute
value of the WAVEFORM register contents for CH2. IPEAK
is 1 times the absolute value of the CH1 Waveform.
Page 18
1. T he phase calibration register resolution has changed to
0.048 from 0.024. T his section calculations have been
changed to reflect this new resolution.
2. Figure 27 updated with new PHC AL range and delay
block rate.
Page 20
Figure 36 T iming was updated.
Page 21
1. T he internal active energy accumulation register is 47 bits
instead of 53 bits. T he equation also shows this change. T his
change is also implemented in the equations of page 25 as
well as Figures 45 and 47 on page 25.
2. T he maximum output frequency is changed to 23Hz.
3. T ext added to explain C F NUM must be less than
C F D E N .
Page 22
1. Figure 39 shows the actual internal register length to be 47
bits. T his change is also on page 23, Figure 41.
2. Line Cycle Energy accumulation mode section changed to
15 bits for L INECY C Register.
Page 26
1. Equation 25 changed to have 2^27 bits for the denomina-
tor.
2. Content of LAENERGY register is 2971.4, and the CF
frequency output in the example calculation is 1398.3 Hz.
3. T he calculation of C F NU M and C F D E N changed
according to the effect of the abovementioned changes.
Page 31
1. T he definition of the SAGCYC a register has changed to
full line cycles. L INEC Y C corrected to say 15 bits and
remains half line cycles.
2. T he PHCAL register description changed to reflect the
new effective length and resolution of the register and default
value of 0D.