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| 型號(hào)： | ADE7169ASTF16-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Single-Phase Energy Measurement IC with 8052 MCU, RTC and LCD driver |
| 中文描述： | ANALOG CIRCUIT, PQFP64 |
| 封裝： | MS-026BCD, LQFP-64 |
| 文件頁(yè)數(shù)： | 61/140頁(yè) |
| 文件大小： | 1359K |
| 代理商： | ADE7169ASTF16-RL |
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Preliminary Technical Data
ADE7169F16
as V
rms
× I
rms
. Equation 28 gives an expression of the
instantaneous power signal in an ac system with a phase shift.
Rev. PrD | Page 61 of 140
( )
v t
2
sin(
)
rms
V
t
ω
=
i
(
t
) =
)
sin(
2
θ
+
ω
t
I
rms
(27)
)
(
)
(
)
(
t
i
t
v
t
p
×
=
p
(
t
) =
)
2
cos(
)
cos(
θ
+
ω
θ
t
I
V
I
V
rms
rms
rms
rms
(28)
The apparent power is defined as V
rms
× I
rms
. This expression is
independent from the phase angle between the current and the
voltage.
Figure 49 illustrates the signal processing in each phase for the
calculation of the apparent power in the ADE7169F16.
V
rms
I
rms
0x1A36E2
APPARENT POWER
SIGNAL (P)
CURRENT RMS SIGNAL – i(t)
VOLTAGE RMS SIGNAL– v(t)
0x1CF68C
MULTIPLIER
0x00
0x1CF68C
0x00
VAGAIN
TO
DIGITALTO FREQUENCY
CONVERTER
Figure 49. Apparent Power Signal Processing
The apparent power signal can be read from the waveform
register by setting the WAVMODE register (0x0D) and setting
the WFSM bit in the Interrupt Enable Register 3 SFR
(MIRQENH, 0xDB). Like the current and voltage channels
waveform sampling modes, the waveform date is available at
sample rates of 27.9 kSPS, 14 kSPS, 7 kSPS, or 3.5 kSPS.
The gain of the apparent energy can be adjusted by using the
multiplier and VAGAIN register (VAGAIN[11:0]). The gain is
adjusted by writing a twos complement, 12-bit word to the
VAGAIN register. Equation 29 shows how the gain adjustment
is related to the contents of the VAGAIN register.
+
1
×
=
12
2
VAGAIN
Power
Apparent
IN
OutputVAGA
(29)
For example, when 0x7FF is written to the VAGAIN register,
the power output is scaled up by 50%. 0x7FF = 2047d, 2047/2
12
= 0.5. Similarly, 0x800 = –2047d (signed twos complement) and
power output is scaled by –50%. Each LSB represents 0.0244%
of the power output. The apparent power is calculated with the
current and voltage rms values obtained in the rms blocks of the
ADE7169F16.
Apparent Power Offset Calibration
Each rms measurement includes an offset compensation
register to calibrate and eliminate the dc component in the rms
value—see Current Channel RMS Calculation and Voltage
channel RMS Calculation sections. The voltage and current
channels rms values are then multiplied together in the
apparent power signal processing. Since no additional offsets
are created in the multiplication of the rms values, there is no
specific offset compensation in the apparent power signal
processing. The offset compensation of the apparent power
measurement is done by calibrating each individual rms
measurement.
Apparent Energy Calculation
The apparent energy is given as the integral of the apparent
power.
∫
=
dt
t
Power
Apparent
Energy
Apparent
)
(
(30)
The ADE7169F16 achieves the integration of the apparent
power signal by continuously accumulating the apparent power
signal in an internal 48-bit register. The apparent energy
register (VAHR[23:0]) represents the upper 24 bits of this
internal register. This discrete time accumulation or summation
is equivalent to integration in continuous time. Equation 31
expresses the relationship
×
=
∑
=
n
→
0
0
)
(
T
T
nT
Power
Apparent
Lim
Energy
Apparent
(31)
where:
n
is the discrete time sample number.
T
is the sample period.
The discrete time sample period (T) for the accumulation
register in the ADE7169F16 is 1.22 μs (5/MCLK).
Figure 50 shows this discrete time integration or accumulation.
The apparent power signal is continuously added to the internal
register. This addition is a signed addition even if the apparent
energy remains theoretically always positive.
The 49 bits of the internal register are divided by VADIV. If the
value in the VADIV register is 0, then the internal apparent
energy register is divided by 1. VADIV is an 8-bit unsigned
register. The upper 24 bits are then written in the 24-bit
apparent energy register (VAHR[23:0]). RVAHR register (24
bits long) is provided to read the apparent energy. This register
is reset to 0 after a read operation.
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