參數(shù)資料
型號(hào)： ADD8754
廠商： Analog Devices, Inc.
英文描述： LCD Panel Power, VCOM, and Gate Modulation
中文描述： 液晶面板電源，威科姆，和門調(diào)制
文件頁(yè)數(shù)： 17/28頁(yè)
文件大?。?/td> 405K
代理商： ADD8754
ADD8754
POWER-UP SEQUENCE
Most LCD panels require that when VIN is applied, LDO_OUT,
VGL, BOOST_OUT, VGH, and VGH_M are established
sequentially, as indicated in Figure 22. ADD8754 provides this
sequence with appropriate capacitors for the VGL and VGH
charge pumps.
Rev. 0 | Page 17 of 28
LDO Input Capacitor Selection
For the input voltage of the ADD8754 LDO regulator (VIN_1),
a local bypass capacitor is recommended. The input capacitor
provides bypassing for the internal amplifier used in the voltage
regulation loop. Use at least a 1 μF low ESR capacitor. Larger
input capacitance and lower ESR provide better supply noise
rejection. Multilayer ceramic chip (MLCC) capacitors provide
the best combination of low ESR and small size.
LDO Output Capacitor Selection
The output capacitor improves the regulator response to sudden
load changes. The output capacitor helps determine the perfor-
mance of any LDO. The ADD8754 LDO requires at least a 2.2 μF
capacitor. Transient response is a function of output capacitance,
in that larger values of output capacitance decrease peak devia-
tions, providing improved transient response for large load
current changes.
VIN
VDPM
VGH
VGL
BOOST_OUT
LDO_OUT
VGH_M
0
SHDN
SHDN THRESHOLD LEVEL
Choose the capacitors by comparing their lead inductance, ESR,
and dissipation factor. Output capacitance affects stability, and a
larger cap provides a greater phase margin for the ADD8754
LDO. MLCC capacitors provide the best combination of low
ESR and small size.
Figure 22. Power-Up Sequence Timing Diagram
LDO Regulator
The ADD8754 low dropout (LDO) regulator has three preset
output voltage settings. As shown in Table 13, by tying the ADJ
pin low, a 3.3 V nominal output is selected. By tying ADJ to the
output voltage, a 2.5 V nominal output is selected. By leaving
ADJ as an open circuit, a nominal voltage of 2.85 V is selected.
Note that the capacitance of some capacitor types show wide
variations over temperature. A good quality dielectric X7R or
better capacitor is recommended.
SHUTDOWN
Applying a TTL high signal to the shutdown pin (tying it to the
VIN_1) turns on all outputs. Pulling SHDN down to 0.4 V or
below (tying it to GND) turns off all outputs. In shutdown
mode, quiescent current is reduced to a typical value of 300 μA.
Table 13. LDO Output Voltage Selection
LDO Output Voltage
2.5 V
2.85 V
3.3 V
ADJ Pin
LDO_OUT
No connection
GND
UVLO
An undervoltage lockout (UVLO) circuit is included with a
built in hysteresis. ADD8754 turns on when VIN_1 rises above
2.8 V and shuts down when VIN_1 falls below 2.6 V.
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