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參數(shù)資料
| 型號： | ADD8754 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | LCD Panel Power, VCOM, and Gate Modulation |
| 中文描述： | 液晶面板電源，威科姆，和門調(diào)制 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 405K |
| 代理商： | ADD8754 |
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ADD8754
V
COM
AMPLIFIER
The output of the V
COM
amplifier is designed to control the
voltage on the V
COM
plane of the LCD display. The V
COM
amplifier is designed to source and sink the capacitive pulse
current and ensure stable operation with high load capacitance.
Input Overvoltage Protection
Whenever the input exceeds the supply voltage, attention must
be paid to the input overvoltage characteristics. When an
overvoltage occurs, the amplifier can be damaged, depending
on the voltage level and the magnitude of the fault current.
When the input voltage exceeds the supply voltage by more
than 0.6 V, the internal pin junctions allow current to flow from
the input to the supplies. This input current is not inherently
damaging to the device, provided it is 5 mA or less.
Short-Circuit Output Conditions
The V
COM
amplifier does not have internal short-circuit protection
circuitry. As a precaution, do not short the output directly to the
positive power supply or to the ground.
Rev. 0 | Page 16 of 28
The delay capacitance in farad is calculated using the following
equation:
CE
= (
Delay Time
) × 0.000238
The RE in ohms is calculated using the following equation:
(
)
5000
302
Load
×
=
e
Capacitanc
Rate
Slew
RE
When the voltage on the VDPM pin is less than the turn-on
threshold value, the CE pin is internally connected to GND to
discharge the delay capacitor.
S1
S2
S3
REF
L
O
G
I
C
GND
S4
VIN_1
GATE HIGH
MOD. CIRCUIT
GND
GND
RAMP
RESISTOR
DELAY
CAPACITOR
CE
RE
V
OUT
/VGH
VDD_1
VGH_M
VGH
VDPM
VFLK
CL
0
GATE PULSE MODULATOR CIRCUIT
The gate pulse modulator is used for LCD applications in which
shaping of the gate high voltage signal improves image quality.
A charge pump is used to generate the on voltage, VGH. A lower
gate voltage level, VDD_1, is desired during the last portion of
the gate’s on time and is provided by VOUT. The integrated gate
pulse modulator circuit provides control over the slope and delay
of the transition between these two TFT on-voltage levels.
Figure 20. Gate Pulse Modulator Functional Block Diagram
The gate pulse modulator circuit has four input pins (VGH,
VDD_1, VDPM, and VFLK) and one output pin (VGH_M).
VFLK is a digital control signal, usually provided by the timing
controller, whose high or low level determines which of the two
input voltages, VGH or VDD_1, is passed through to VGH_M.
The gate high modulator circuit becomes active when the voltage
on pin VDPM exceeds the turn-on threshold value of 2.2 V.
ENABLE – VDPM
CONTROL SIGNAL – VFLK
OUTPUT SIGNAL – VGH_M
WITH LOAD
CAPACITANCE CL
LOW
LOW
LOW
T1
T2
T1
T2
DELAY CONTROLLED
BY CE
VGH
VDD_1
SLOPE CONTROLLED BY RE
0
When the control voltage VFLK switches from logic low to logic
high during normal operation with VDPM at logic high (see
Figure 21), the output voltage VGH_M transitions from VDD_1
to VGH. When the control voltage VFK switches from logic
high to logic low, the output voltage VGH_M transitions from
VGH to VDD_1 after a time delay determined by the size of a
capacitor from the CE pin to the GND and a slew rate
determined by the size of resistor from the RE pin to the GND.
Figure 21. Gate Pulse Modulator Timing Diagram
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