- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10737 > ADCMP607BCPZ-WP (Analog Devices Inc)IC COMP TTL/CMOS 1CHAN 12-LFCSP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADCMP607BCPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN 12-LFCSP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | CML，補(bǔ)充型，滿擺幅 |
| 電壓 - 電源，單路/雙路(±)： | 2.5 V ~ 5.5 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 2.5V |
| 電流 - 輸入偏壓（最小值）： | 5µA @ 2.5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 50mA |
| 電流 - 靜態(tài)（最大值）： | 1.5mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 50dB CMRR，50dB PSRR |
| 傳輸延遲（最大）： | 2.1ns |
| 磁滯： | 100µV |
| 工作溫度： | -40°C ~ 125°C |
| 封裝/外殼： | 12-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 - 晶粒 |
ADCMP606/ADCMP607
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP606/ADCMP607 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
tH
tPDL
tPLOH
tF
VIN
VOD
tS
tPL
50%
Q OUTPUT
tPDH
tPLOL
tR
05
91
7-
0
25
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the 20%
and 80% points.
tH
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input signal
must remain unchanged to be acquired and held at the outputs.
tPDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPL
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal
change.
tPLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the 20%
and 80% points.
tS
Minimum setup time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| VI-JNR-MY-F4 | CONVERTER MOD DC/DC 7.5V 50W |
| VI-BWY-MW-B1 | CONVERTER MOD DC/DC 3.3V 66W |
| VI-JNR-MY-F2 | CONVERTER MOD DC/DC 7.5V 50W |
| VI-BWW-MY-B1 | CONVERTER MOD DC/DC 5.5V 50W |
| VI-JNR-MY-F1 | CONVERTER MOD DC/DC 7.5V 50W |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADCMP608 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP608_07 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP608BKSZ-R2 | 功能描述:IC COMP TTL/CMOS R-R SGL SC70-6 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:25 系列:- 類型:帶電壓基準(zhǔn) 元件數(shù):4 輸出類型:CMOS，開路漏極，TTL 電壓 - 電源，單路/雙路(±):2 V ~ 11 V，±1 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:10mV @ 5V 電流 - 輸入偏壓（最小值）:- 電流 - 輸出（標(biāo)準(zhǔn)）:0.015mA @ 5V 電流 - 靜態(tài)（最大值）:8.5µA CMRR, PSRR（標(biāo)準(zhǔn)）:80dB CMRR，80dB PSRR 傳輸延遲（最大）:12µs 磁滯:50mV 工作溫度:0°C ~ 70°C 封裝/外殼:16-DIP（0.300"，7.62mm） 安裝類型:通孔 包裝:管件 |
| ADCMP608BKSZ-REEL | 制造商:AD 制造商全稱:Analog Devices 功能描述:Rail-to-Rail, Fast, Low Power 2.5 V to 5.5 V, Single-Supply TTL/CMOS Comparator |
| ADCMP608BKSZ-REEL7 | 功能描述:IC COMPARATOR TTL/CMOS SC70-6 RoHS:是 類別:集成電路 (IC) >> 線性 - 比較器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 類型:通用 元件數(shù):1 輸出類型:CMOS，開路集電極，TTL 電壓 - 電源，單路/雙路(±):2.7 V ~ 5.5 V 電壓 - 輸入偏移（最小值）:7mV @ 5V 電流 - 輸入偏壓（最小值）:0.25µA @ 5V 電流 - 輸出（標(biāo)準(zhǔn)）:84mA @ 5V 電流 - 靜態(tài)（最大值）:120µA CMRR, PSRR（標(biāo)準(zhǔn)）:- 傳輸延遲（最大）:600ns 磁滯:- 工作溫度:-40°C ~ 85°C 封裝/外殼:SC-74A，SOT-753 安裝類型:表面貼裝 包裝:剪切帶 (CT) 產(chǎn)品目錄頁面:1268 (CN2011-ZH PDF) 其它名稱:*LMV331M5*LMV331M5/NOPBLMV331M5CT |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。