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參數(shù)資料
| 型號(hào)： | ADCMP573BCPZ-WP |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 5/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL 3.3-5 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類(lèi)型： | 帶鎖銷(xiāo) |
| 元件數(shù)： | 1 |
| 輸出類(lèi)型： | 補(bǔ)充型，PECL |
| 電壓 - 電源，單路/雙路(±)： | 3.1 V ~ 5.4 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 25µA @ 3.3V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 35mA |
| 電流 - 靜態(tài)（最大值）： | 80mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 65dB CMRR，74dB PSRR |
| 傳輸延遲（最大）： | 0.165ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤(pán)，CSP |
| 安裝類(lèi)型： | 表面貼裝 |
| 包裝： | 托盤(pán) - 晶粒 |
| 配用： | EVAL-ADCMP573BCPZ-ND - BOARD EVALUATION ADCMP573BCP |
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ADCMP572/ADCMP573
Rev. A | Page 13 of 16
TIMING INFORMATION
Figure 29 illustrates the ADCMP572/ADCMP573 compare and latch timing relationships. Table 4 provides definitions of the terms
shown in the figure.
50%
VN ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
04409-003
Figure 29. System Timing Diagram
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to output high delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input to output low delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch enable to output high delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch enable to output low delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum hold time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum latch enable pulse width
Minimum time that the latch enable signal must be high to acquire an input signal
change.
tS
Minimum setup time
Minimum time before the negative transition of the latch enable signal that an input
signal change must be present to be acquired and held at the outputs.
tR
Output rise time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output fall time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VOD
Voltage overdrive
Difference between the input voltages VA and VB.
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