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參數(shù)資料
| 型號(hào)： | ADCMP573BCPZ-WP |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC COMPARATOR PECL 3.3-5 16LFCSP |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 1 |
| 輸出類型： | 補(bǔ)充型，PECL |
| 電壓 - 電源，單路/雙路(±)： | 3.1 V ~ 5.4 V |
| 電壓 - 輸入偏移（最小值）： | 2mV @ 3.3V |
| 電流 - 輸入偏壓（最小值）： | 25µA @ 3.3V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 35mA |
| 電流 - 靜態(tài)（最大值）： | 80mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 65dB CMRR，74dB PSRR |
| 傳輸延遲（最大）： | 0.165ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 16-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 - 晶粒 |
| 配用： | EVAL-ADCMP573BCPZ-ND - BOARD EVALUATION ADCMP573BCP |
ADCMP572/ADCMP573
Rev. A | Page 9 of 16
APPLICATION INFORMATION
POWER/GROUND LAYOUT AND BYPASSING
The ADCMP572/ADCMP573 comparators are very high speed
SiGe devices. Consequently, it is essential to use proper high
speed design techniques to achieve the specified performance.
Of critical importance is the use of low impedance supply
planes, particularly the output supply plane (VCCO) and the
ground plane (GND). Individual supply planes are recom-
mended as part of a multilayer board. Providing the lowest
inductance return path for switching currents ensures the best
possible performance in the target application.
It is important to adequately bypass the input and output
supplies. A 1 μF electrolytic bypass capacitor should be placed
within several inches of each power supply pin to ground. In
addition, multiple high quality 0.01 μF bypass capacitors should
be placed as close as possible to each of the VCCI and VCCO
supply pins and should be connected to the GND plane with
redundant vias. High frequency bypass capacitors should be
carefully selected for minimum inductance and ESR. Parasitic
layout inductance should be avoided to maximize the
effectiveness of the bypass at high frequencies.
If the input and output supplies are connected separately such
that VCCI ≠ VCCO, care should be taken to bypass each of these
supplies separately to the GND plane. A bypass capacitor
should not be connected between them. It is recommended that
the GND plane separate the VCCI and VCCO planes when the
circuit board layout is designed to minimize coupling between
the two supplies and to take advantage of the additional bypass
capacitance from each respective supply to the ground plane.
This enhances the performance when split input/output
supplies are used. If the input and output supplies are connected
together for single-supply operation such that VCCI = VCCO,
coupling between the two supplies is unavoidable; however,
every effort should be made to keep the supply plane adjacent
to the GND plane to maximize the additional bypass
capacitance this arrangement provides.
CML/RSPECL OUTPUT STAGE
Specified propagation delay dispersion performance can be
achieved only by using proper transmission line terminations.
The outputs of the ADCMP572 are designed to directly drive
400 mV into 50 Ω cable, microstrip, or strip line transmission
lines properly terminated to the VCCO supply plane. The CML
output stage is shown in the simplified schematic diagram of
Figure 15. The outputs are each back terminated with 50 Ω for
best transmission line matching. The RSPECL outputs of the
ADCMP573 are illustrated in Figure 16 and should be
terminated to VCCO 2 V. As an alternative, Thevenin
equivalent termination networks can be used in either case if
the direct termination voltage is not readily available. If high
speed output signals must be routed more than a centimeter,
microstrip or strip line techniques are essential to ensure proper
transition times and to prevent output ringing and pulse width
dependent propagation delay dispersion. For the most timing
critical applications where transmission line reflections pose the
greatest risk to performance, the ADCMP572 provides the best
match to 50 Ω output transmission paths.
Q
16mA
50
Ω
Q
04409-037
VCCO
GND
Figure 15. Simplified Schematic Diagram of
the ADCMP572 CML Output Stage
04409-038
VCCO
GND
Q
Figure 16. Simplified Schematic Diagram of
the ADCMP573 RSPECL Output Stage
USING/DISABLING THE LATCH FEATURE
The latch inputs (LE/LE) are active low for latch mode and are
internally terminated with 50 Ω resistors to Pin 8. This pin
corresponds to and is internally connected to the VCCO supply
for the CML-compatible ADCMP572. With the aid of these
resistors the ADCMP572 latch function can be disabled by
connecting the LE pin to GND with an external pull-down
resistor and leaving the LE pin unconnected. To avoid excessive
power dissipation, the resistor should be 750 Ω when VCCO =
3.3 V, and 1.2 kΩ when VCCO = 5.2 V. In the PECL-compatible
ADCMP573, the VTT pin should be connected externally to the
PECL termination supply at VCCO – 2 V. The latch can then be
disabled by connecting the LE pin to VCCO with an external
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