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參數(shù)資料
| 型號(hào)： | ADCMP567BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/17頁 |
| 文件大小： | 0K |
| 描述： | IC COMP DUAL ULTRA-FAST 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 帶鎖銷 |
| 元件數(shù)： | 2 |
| 輸出類型： | 補(bǔ)充型，差分，開路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 24µA @ 5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 20mA，95mA，18mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 69dB CMRR |
| 傳輸延遲（最大）： | 0.3ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 安裝類型： | 表面貼裝 |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP567BCPZ-ND - BOARD EVALUATION ADCMP567BCP |
ADCMP567
Rev. 0 | Page 8 of 16
TIMING INFORMATION
50%
VREF ± VOS
50%
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
LATCH ENABLE
tH
tPDL
tPDH
tPLOH
tPLOL
tR
tF
VIN
VOD
tS
tPL
03633-0-003
Figure 3. System Timing Diagram
The timing diagram in Figure 3 shows the ADCMP567 compare
and latch features. Table 4 describes the terms in the diagram.
Table 4. Timing Descriptions
Symbol
Timing
Description
tPDH
Input to output
high delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output low-to-high transition
tPDL
Input to output
low delay
Propagation delay measured from
the time the input signal crosses
the reference (± the input offset
voltage) to the 50% point of an
output high-to-low transition
tPLOH
Latch enable
to output high
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output low-
to-high transition
tPLOL
Latch enable
to output low
delay
Propagation delay measured from
the 50% point of the Latch Enable
signal low-to-high transition to
the 50% point of an output high-
to-low transition
Symbol
Timing
Description
tH
Minimum
hold time
Minimum time after the negative
transition of the Latch Enable
signal that the input signal must
remain unchanged to be acquired
and held at the outputs
tPL
Minimum
latch enable
pulsewidth
Minimum time that the Latch
Enable signal must be high to
acquire an input signal change
tS
Minimum
setup time
Minimum time before the
negative transition of the Latch
Enable signal that an input signal
change must be present to be
acquired and held at the outputs
tR
Output rise
time
Amount of time required to
transition from a low to a high
output as measured at the 20%
and 80% points
tF
Output fall
time
Amount of time required to
transition from a high to a low
output as measured at the 20%
and 80% points
VOD
Voltage
overdrive
Difference between the
differential input and reference
input voltages
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