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參數(shù)資料
| 型號(hào)： | ADCMP567BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大小： | 0K |
| 描述： | IC COMP DUAL ULTRA-FAST 32LFCSP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類(lèi)型： | 帶鎖銷(xiāo) |
| 元件數(shù)： | 2 |
| 輸出類(lèi)型： | 補(bǔ)充型，差分，開(kāi)路發(fā)射極，PECL |
| 電壓 - 電源，單路/雙路(±)： | ±4.75 V ~ 5.25 V |
| 電壓 - 輸入偏移（最小值）： | 5mV @ 5V |
| 電流 - 輸入偏壓（最小值）： | 24µA @ 5V |
| 電流 - 輸出（標(biāo)準(zhǔn)）： | 30mA |
| 電流 - 靜態(tài)（最大值）： | 20mA，95mA，18mA |
| CMRR, PSRR（標(biāo)準(zhǔn)）： | 69dB CMRR |
| 傳輸延遲（最大）： | 0.3ns |
| 磁滯： | ±1mV |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 32-VFQFN 裸露焊盤(pán)，CSP |
| 安裝類(lèi)型： | 表面貼裝 |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 764 (CN2011-ZH PDF) |
| 配用： | EVAL-ADCMP567BCPZ-ND - BOARD EVALUATION ADCMP567BCP |
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ADCMP567
Rev. 0 | Page 6 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
03632-0-002
PIN 1
INDICATOR
VEE
24
23 NC
22 VEE
21 VCC
GND
–INA
+INA
32
GN
D
20 VCC
19 VEE
18 NC
17 VEE
GND
9
LEB
10
LEB
11
NC
12
V
DD
13
14
QB
15
V
DD
16
VCC
+INB
–INB
GND
1
2
3
4
5
6
7
8
31
LEA
30
LEA
NC
29
27
QA
26
QA
25
V
DD
28
V
DD
NC = NO CONNECT
ADCMP567
TOP VIEW
(Not to Scale)
QB
Figure 2. ADCMP567 Pin Configuration
Table 3. ADCMP567 Pin Descriptions
Pin No.
Mnemonic
Function
1
GND
Analog Ground
2
INA
Inverting analog input of the differential input stage for Channel A. The inverting A input must be driven
in conjunction with the noninverting A input.
3
+INA
Noninverting analog input of the differential input stage for Channel A. The noninverting A input must
be driven in conjunction with the inverting A input.
4
VCC
Positive Supply Terminal
5
VCC
Positive Supply Terminal
6
+INB
Noninverting analog input of the differential input stage for Channel B. The noninverting B input must
be driven in conjunction with the inverting B input.
7
INB
Inverting analog input of the differential input stage for Channel B. The inverting B input must be driven
in conjunction with the noninverting B input.
8
GND
Analog Ground
9
GND
Analog Ground
10
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic low), the
output will track changes at the input of the comparator. In the latch mode (logic high), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
11
LEB
One of two complementary inputs for Channel B Latch Enable. In the compare mode (logic high), the
output will track changes at the input of the comparator. In the latch mode (logic low), the output will
reflect the input state just prior to the comparator’s being placed in the latch mode. LEB must be driven
in conjunction with LEB.
12
NC
No Connect. Leave pin unconnected.
13
VDD
Logic Supply Terminal
14
QB
One of two complementary outputs for Channel B. QB will be at logic low if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
15
QB
One of two complementary outputs for Channel B. QB will be at logic high if the analog voltage at the
noninverting input is greater than the analog voltage at the inverting input (provided the comparator is
in the compare mode). See the LEB description (Pin 11) for more information.
16
VDD
Logic Supply Terminal
17
VEE
Negative Supply Terminal
18
NC
No Connect. Leave pin unconnected.
19
VEE
Negative Supply Terminal
20
VCC
Positive Supply Terminal
21
VCC
Positive Supply Terminal
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