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參數(shù)資料
| 型號： | ADCLK954BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK BUFFER MUX 2:12 40LFCSP |
| 標(biāo)準(zhǔn)包裝： | 750 |
| 系列： | SIGe |
| 類型： | 扇出緩沖器（分配），多路復(fù)用器 |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:12 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | LVPECL |
| 頻率 - 最大： | 4.8GHz |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 40-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 40-LFCSP-VQ（6x6） |
| 包裝： | 帶卷 (TR) |
ADCLK954
Rev. B | Page 3 of 12
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Typical (Typ column) values are given for VCC VEE = 3.3 V and TA = 25°C, unless otherwise noted. Minimum (Min column) and maximum
(Max column) values are given over the full VCC VEE = 3.3 V ± 10% and TA = 40°C to +85°C variation, unless otherwise noted.
Table 1. Clock Inputs and Outputs
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
DC INPUT CHARACTERISTICS
Input Common-Mode Voltage
VICM
VEE + 1.5
VCC 0.1
V
Input Differential Range
VID
0.4
3.4
V p-p
±1.7 V between input pins
Input Capacitance
CIN
0.4
pF
Input Resistance
Single-Ended Mode
50
Ω
Differential Mode
100
Ω
Common Mode
50
kΩ
Open VTx
Input Bias Current
20
μA
Hysteresis
10
mV
DC OUTPUT CHARACTERISTICS
Output Voltage High Level
VOH
VCC 1.26
VCC 0.76
V
50 Ω to (VCC 2.0 V)
Output Voltage Low Level
VOL
VCC 1.99
VCC 1.54
V
50 Ω to (VCC 2.0 V)
Output Voltage, Single Ended
VO
610
960
mV
VOH VOL, output static
Reference Voltage
VREF
Output Voltage
(VCC + 1)/2
V
500 μA to +500 μA
Output Resistance
235
Ω
Table 2. Timing Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Test Conditions/Comments
AC PERFORMANCE
Maximum Output Frequency
4.5
4.8
GHz
See Figure 4 for differential output voltage vs.
frequency, > 0.8 V differential output swing
Output Rise Time
tR
40
75
90
ps
20% to 80% measured differentially
Output Fall Time
tF
40
75
90
ps
Propagation Delay
tPD
175
210
245
ps
VICM = 2 V, VID = 1.6 V p-p
Temperature Coefficient
50
fs/°C
Output-to-Output Skew1
9
25
ps
Part-to-Part Skew
45
ps
VID = 1.6 V p-p
Additive Time Jitter
Integrated Random Jitter
28
fs rms
BW = 12 kHz 20 MHz, CLK = 1 GHz
Broadband Random Jitter2
75
fs rms
VID = 1.6 V p-p, 8 V/ns, VICM = 2 V
Crosstalk-Induced Jitter3
90
fs rms
CLOCK OUTPUT PHASE NOISE
Absolute Phase Noise
Input slew rate > 1 V/ns (see Figure 11, the
phase noise plot, for more details)
fIN = 1 GHz
119
dBc/Hz
@100 Hz offset
134
dBc/Hz
@1 kHz offset
145
dBc/Hz
@10 kHz offset
150
dBc/Hz
@100 kHz offset
150
dBc/Hz
>1 MHz offset
1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature.
2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method.
3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs.
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