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參數(shù)資料
| 型號(hào)： | ADCLK846BCPZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK BUFFER 1:6 1.2GHZ 24LFCSP |
| 設(shè)計(jì)資源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類(lèi)型： | 扇出緩沖器（分配） |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:6 |
| 差分 - 輸入:輸出： | 是/是 |
| 輸入： | CML，CMOS，HSTL，LVDS，LVPECL |
| 輸出： | CMOS，LVDS |
| 頻率 - 最大： | 1.2GHz |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-VFQFN 裸露焊盤(pán)，CSP |
| 供應(yīng)商設(shè)備封裝： | 24-LFCSP-VQ（4x4） |
| 包裝： | 帶卷 (TR) |
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ADCLK846
Rev. B | Page 11 of 16
FUNCTIONAL DESCRIPTION
The ADCLK846 clock input is distributed to all output channels.
Each channel bank is pin programmable for either LVDS or
CMOS levels. This allows the selection of multiple logic
configurations ranging from 6 LVDS to 12 CMOS outputs,
along with other combinations using both types of logic.
CLOCK INPUTS
The differential inputs of the ADCLK846 are internally self-
biased. The clock inputs have a resistor divider, which sets the
common-mode level for the inputs. The complementary inputs
are biased about 30 mV lower than the true input to avoid
oscillations if the input signal ceases. See Figure 20 for
the equivalent input circuit.
The inputs can be ac-coupled or dc-coupled. Table 8 displays
a guide for input logic compatibility. If a single-ended input is
desired, this can be accommodated by ac or dc coupling to one
side of the differential input. Bypass the other input to ground
by a capacitor.
Note that jitter performance degrades with low input slew rate,
different termination schemes.
9k
9.5k
9k
8.5k
VS
CLK
GND
07
22
6-
0
23
Figure 20. ADCLK846 Input Stage
AC-COUPLED APPLICATIONS
When ac coupling is desired, the ADCLK846 offers two
options. The first option requires no external components
(excluding the dc blocking capacitor); it allows the user to
couple the reference signal onto the clock input pins (see
The second option allows the use of the VREF pin to set the dc
bias level for the ADCLK846. The VREF pin can be connected
to CLK and CLK through resistors. This method allows lower
impedance termination of signals at the ADCLK846 (see
The internal bias resistors are still in parallel with the external
biasing. However, the relatively high impedance of the internal
resistors allows the external termination to VREF to dominate.
This is also useful if it is not desirable to offset the inputs slightly
as previously mentioned using only the internal biasing.
Table 8. Input Logic Compatibility
Supply (V)
Logic
Common Mode (V)
Output Swing (V)
AC-Coupled
DC-Coupled
3.3
CML
2.9
0.8
Yes
Not allowed
2.5
CML
2.1
0.8
Yes
Not allowed
1.8
CML
1.4
0.8
Yes
3.3
CMOS
1.65
3.3
Not allowed
2.5
CMOS
1.25
2.5
Not allowed
1.8
CMOS
0.9
1.8
Yes
1.5
HSTL
0.75
Yes
LVDS
1.25
0.4
Yes
3.3
LVPECL
2.0
0.8
Yes
Not allowed
2.5
LVPECL
1.2
0.8
Yes
1.8
LVPECL
0.5
0.8
Yes
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