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參數(shù)資料
| 型號： | ADC71JG |
| 英文描述： | 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 7/9頁 |
| 文件大?。?/td> | 96K |
| 代理商： | ADC71JG |
7
ADC71
27
26
Bipolar
Offset
25
24
22
Comparator
to Logic
From D/A
Converter
Direct
Input
R
1
5k
Comp
In
V
REF
R
2
5k
6.3k
30
28
22
21
19
1μF
+5VDC
Analog
Common
–15VDC
Digital
Common
+15VDC
1μF
+
+
+
1μF
FIGURE 8. Recommended Power Supply Decoupling.
LAYOUT AND OPERATING INSTRUCTIONS
Layout Precautions
Analog and digital common are not connected internally in
the ADC71 but should be connected together as close to the
unit as possible, preferably to a large plane under the ADC.
If these grounds must be run separately, use wide conductor
patterns and a 0.01
μ
F to 0.1
μ
F non-polarized bypass capaci-
tor between analog and digital commons at the unit. Low
impedance analog and digital commons returns are essential
for low noise performance. Coupling between analog inputs
and digital lines should be minimized by careful layout. The
comparator input (Pin 27) is extremely sensitive to noise.
Any connection to this point should be as short as possible
and shielded by Analog Common patterns.
POWER SUPPLY DECOUPLING
The power supplies should be bypassed with tantalum ca-
pacitors as shown in Figure 8 to obtain noise free operation.
These capacitors should be located close to the ADC.
INPUT SCALING
The analog input should be scaled as close to the maximum
input signal range as possible in order to utilize the maxi-
mum signal resolution of the A/D converter. Connect the
input signal as shown in Table II. See Figure 9 for circuit
details.
CONNECT
INPUT
SIGNAL
TO PIN
INPUT
SIGNAL
RANGE
CONNECT
PIN 26
TO PIN
CONNECT
PIN 24
TO
OUTPUT
CODE
±
10V
±
5V
±
2.5V
0 to +5V
0 to +10V
0 to +20V
COB or CTC
(1)
COB or CTC
(1)
COB or CTC
(1)
CSB
CSB
CSB
27
27
27
22
22
22
Input Signal
Open
Pin 27
Pin 27
Open
Input Signal
24
25
25
25
25
24
NOTE: (1) Obtained by inverting MSB pin 1.
TABLE II. ADC71 Input Scaling Connections.
OPTIONAL EXTERNAL GAIN
AND OFFSET ADJUSTMENTS
Gain and Offset errors may be trimmed to zero using
external gain and offset trim potentiometers connected to the
ADC as shown in Figure 6 and 7. Multiturn potentiometers
with 100ppm/
°
C or better TCRs are recommended for mini-
mum drift over temperature and time. These pots may be any
value from 10k
to 100k
. All resistors should be 20%
carbon or better. Pin 29 (Gain Adjust) and Pin 27 (Offset
Adjust) may be left open of no external adjustment is
required.
ADJUSTMENT PROCEDURE
OFFSET — Connect the Offset potentiometer (make sure R
1
is as close to pin 27 as possible) as shown in Figure 6. Sweep
the input through the end point transition voltage that should
cause an output transition to all bits Off (E
IN
).
Adjust the Offset potentiometer until the actual end point
transition voltage occurs at E
. The ideal transition voltage
values of the input are given in Table I.
GAIN — Connect the Gain Adjust potentiometer as shown
in Figure 7. Sweep the input through the end point transition
voltage that should cause an output transition to all bits on
(E
IN
). Adjust the Gain potentiometer until the actual end
point transition voltage occurs at E
IN
.
Table I details the transition voltage levels required.
CONVERT COMMAND CONSIDERATIONS
Convert command resets the converter whenever taken high.
This insures a valid conversion on the first conversion after
power-up.
Convert command must stay low during a conversion unless
it is desired to reset the converter during a conversion.
ADDITIONAL CONNECTIONS REQUIRED
The ADC71 may be operated at faster speeds by connecting
the Short-Cycle Input, pin 32, as shown in Table III. Conver-
sion speeds, linearity, and resolutions are shown for refer-
ence.
FIGURE 9. ADC71 Input Scaling Circuit.
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