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參數(shù)資料
| 型號： | ADC71JG |
| 英文描述： | 16-Bit ANALOG-TO-DIGITAL CONVERTER |
| 中文描述： | 16位模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大小： | 96K |
| 代理商： | ADC71JG |
6
ADC71
FIGURE 5. ADC71 Connections for:
±
10V Analog Input, 14-Bit Resolution (Short-Cycled), Parallel Data Output.
FIGURE 6. Two Methods of Connecting Optional Offset
Adjust with a 0.4% of FSR of Adjustment.
FIGURE 7. Connecting Optional Gain Adjust with a 0.2%
Range of Adjustment.
SERIAL DATA
Two straight binary (complementary) codes are available on
the serial output line: CSB and COB. The serial data is
available only during conversion and appears with MSB
occurring first. The serial data is synchronous with the
internal clock as shown in the timing diagrams of Figures 2
and 3. The LSB and transition values shown in Table I also
apply to the serial data output except for the CTC code.
DISCUSSION
OF SPECIFICATIONS
The ADC71 is specified to provide critical performance
criteria for a wide variety of applications. The most critical
specifications for an A/D converter are linearity, drift, gain
and offset errors. This ADC is factory-trimmed and tested
for all critical key specifications.
GAIN AND OFFSET ERROR
Initial Gain and Offset errors are factory-trimmed to typi-
cally
±
0.1% of FSR (typically
±
0.05% for unipolar offset) at
25
°
C. These errors may be trimmed to zero by connecting
external trim potentiometers as shown in Figures 6 and 7.
POWER SUPPLY SENSITIVITY
Changes in the DC power supplies will affect accuracy. The
power supply sensitivity is specified for
±
0.003% of FSR/
%
V
for
±
15V supplies and
±
0.001% of FSR/%
for +5
supplies. Normally, regulated power supplies with 1% or
less ripple are recommended for use with this ADC. See
Layout Precautions, Power Supply Decoupling and Figure
8.
270k
MSB 1
2
3
4
5
6
7
8
9
10
11
12
13
15
14
NC 16
32
31
30
29
28
27
26
25
24
23
22
21
20
18
19
17
L
Dotted Lines
Are External
Connections
0.01μF
(1)
Analog Input
±10V
1.8M
Gain
Adjust
10k
to
100k
Offset
Adjust
Status Output to
Control Logic
NC
+5VDC
+15VDC
1μF
1μF
Analog
Common
–15VDC
Digital
Common
Convert Command From
Control Logic
NOTE: (1) Capacitor should be connected even if external gain adjust is not used.
10k
to
100k
Bipolar
Offset
ADC71
1μF
NC
+
+
+
+15VDC
–15VDC
10k
to 100k
Offset Adjust
22k
(b)
27
+15VDC
–15VDC
10k
to 100k
Offset Adjust
(a)
Comparator In
27
Comparator In
180k
180k
1.8M
22
+15VDC
–15VDC
Gain Adjust
0.01μF
29
Analog Common
270k
10k
to 100k
Gain Adjust
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相關(guān)代理商/技術(shù)參數(shù) |
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