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| 型號： | ADC1215S065HN |
| 廠商： | NXP Semiconductors N.V. |
| 元件分類： | 外設及接口 |
| 英文描述： | Single 12-bit ADC 65 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| 封裝： | ADC1215S065HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618-6.html<1<Always Pb-free,;ADC1215S065HN/C1<SOT618-6 (HVQFN40)|<<http://www.nxp.com/packages/SOT618 |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 292K |
| 代理商： | ADC1215S065HN |
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ADC1215S_SER
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 13 January 2011
18 of 42
NXP Semiconductors
ADC1215S series
Single 12-bit ADC; input buffer; CMOS or LVDS DDR digital output
11.1.2
Operating mode selection
The active ADC1215S operating mode (Power-up, Power-down or Sleep) can be selected
via the SPI interface (see
Figure 24
) or using pins PWD and OE in Pin control mode, as
described in
Table 10
.
Table 10.
Pin PWD
0
0
1
1
11.1.3
Selecting the output data standard
The output data standard (CMOS or LVDS DDR) can be selected via the SPI interface
(see
Table 23
) or using pin ODS in Pin control mode. LVDS DDR is selected when ODS is
HIGH, otherwise CMOS is selected.
11.1.4
Selecting the output data format
The output data format can be selected via the SPI interface (offset binary, two’s
complement or gray code; see
Table 23
) or using pin DFS in Pin control mode (offset
binary or two’s complement). Offset binary is selected when DFS is LOW. When DFS is
HIGH, two’s complement is selected.
11.2 Analog inputs
11.2.1
Input stage
The analog input of the ADC1215S supports a differential or a single-ended input drive.
Optimal performance is achieved using differential inputs. The ADC inputs are internally
biased and need to be decoupled.
The full-scale analog input voltage range is configurable between 1 V (p-p) and 2 V (p-p)
via a programmable internal reference (see
Section 11.3
and
Table 21
).
The equivalent circuit of the input buffer followed by the Sample and Hold (S/H) input
stage, including ElectroStatic Discharge (ESD) protection and circuit and package
parasitics, is shown in
Figure 14
.
Operating mode selection via pin PWD and OE
Pin OE
0
1
0
1
Operating mode
Power-up
Power-up
Sleep
Power-down
Output high-Z
no
yes
yes
yes
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| ADC1215S065HN | Single 12-bit ADC 65 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
| ADC1215S080HN | Single 12-bit ADC 80 Msps with Input Buffer CMOS or LVDS DDR digital outputs |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| ADC1215S065HN/C1 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Single 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps with input buffer; CMOS or LVDS DDR digital outputs |
| ADC1215S065HN/C1,5 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC SGL 12BIT ADC 65MSPS IN BUF CMOS/LVDS DDR RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| ADC1215S065HN-C1 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Bulk |
| ADC1215S065HN-C18 | 制造商:Integrated Device Technology Inc 功能描述:HVQFN40 - Tape and Reel |
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