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參數(shù)資料
| 型號： | ADC-305 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; No. of Contacts:66; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:19-35 |
| 中文描述： | 8位，20MHz的的CMOS A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 3/6頁 |
| 文件大?。?/td> | 193K |
| 代理商： | ADC-305 |
ADC-305
Figure 3. Equivalent Circuits
Figure 2. Timing Diagram
3
These values may differ from one device to another. Voltage
changes on the +5V supply have a direct influence on the
performance of the device. The use of external references is
recommended for applications sensitive to gain error.
External Reference Mode
Tie V
RB
to AGND, and apply +2V to V
RT
to use at 0 to +2V
input voltage range. The reference resistance between V
RB
and V
RT
is about 300 ohms. It is important to make the
output impedance of the reference source small enough
while, at the same time, keeping sufficient drive capacity.
Insert a 0.1μF bypass ceramic chip capacitor between V
RT
and GND to minimize the effect of the 20MHz clock
running nearby. See Figure 5.
5. Logic inputs are CMOS compatible. Normally a series 74HC
is used as a driver. It is recommended to pull up to +5V if
the device is driven with TTL.
6. The start convert (A/D CLK) pulse can be a 50% duty cycle
clock. Both T
PW1
and T
PW0
are 25ns minimum. A slightly
longer T
PW1
will improve linearity of the system for higher
frequency input signals.
7. The digital data outputs are 3-state and TTL compatible. To
enable the 3-state outputs, connect the OUTPUT ENABLE
(pin 1) to GND. To disable, connect it to +5V. It is
recommended that the data outputs be latched and buffered
through output registers.
8. Maximum 30ns (18ns typical) after the rising edge of the
Nth conversion pulse, the result of the (N-3) conversion can
be obtained. Data is stored firmly in an output register, such
as an 74LS574, using the rising edge of a start convert
pulse as a trigger. The (N–4) data is stored in this case. See
the timing diagrams, Figure 2 and 4.
9. The 20MHz sampling rate is guaranteed. It is not
recommended to use this device at sampling rates slower
than 500kHz because the droop characteristics of the
internal sample and holds will then exceed the limit
required to maintain the specified accuracy of the device.
Ta
T
PW1
T
PW0
N
N+1
N+2
N+3
N+4
N
N+1
N-1
N-2
N-3
ANALOG
INPUT
CLOCK
DATA
OUTPUT
Td= 30ns max.
22
23
17
16
+DV
S
Digital Output Circuit, Bit1 through Bit 8
Analog Input
Generates +0.6V
when shorted with V
B
Generates +2.6V
when shorted with V
T
19
Voltage Reference (V
RT
,V
RB
)
Equivalent Circuit
Equivalent Circuit for OE and A/D CLK
OE - Low data is output when high digital
output pins turn to high impedance.
+AV
S
V
RBS
V
RTS
+DGND
OE
A/D CLK
+AV
S
V
IN
AGND
+AV
S
AGND
V
RT
V
RB
AGND
+DV
S
DGND
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