參數(shù)資料
型號： ADC-305
廠商： Electronic Theatre Controls, Inc.
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:66; Series:LJT00R; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:19; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:19-35
中文描述： 8位，20MHz的的CMOS A / D轉(zhuǎn)換
文件頁數(shù)： 2/6頁
文件大小： 193K
代理商： ADC-305
ADC-305
TECHNICAL NOTES
1. The ADC-305 has separate +AV
S
and +DV
S
pins. It is
recommended that both +AV
S
and +DV
S
be powered from a
single supply since a time lag between start up of separate
supplies could induce latch up. Other external logic circuits
must be powered from a separate digital supply. +DV
S
(pins
11 and 13) and +AVs (pins 14, 15 and 18) should be tied
together externally. DGND (pins 2 and 24) and AGND (pins
20 and 21) should also be tied together externally. Power
supply grounds must be connected at one point to the
ground plane directly beneath the device. Digital returns
should not flow through analog grounds.
2. Bypass all power lines to ground with a 0.1μF ceramic chip
capacitor in parallel with a 47μF electrolytic capacitor.
Locate the bypass capacitor as close to the unit as
possible.
3. Even though the analog input capacitance is a low 15pF, it
is recommended that high frequency input be provided via
a high speed buffer amplifier. A parasitic oscillation may be
generated when a high speed amplifier is used. A 75 ohm
resister inserted between the output of an amplifier and the
analog input of the ADC-305 will improve the situation. A
resistor larger than 100 ohms may degrade linearity.
4. The input voltage range is determined by voltages applied
to V
RB
(Reference Bottom) and V
RT
(Reference Top). Keep
to the following equations;
0V
≤
V
RB
≤
V
RT
≤
2.8V
1.8V
≤
V
RT
–V
RB
≤
2.8V
The analog input range is normally 2Vp-p.
Self Bias Mode
a. Tie V
RB
to V
RBS
, and tie V
RT
to V
RTS
respectively. The analog
input range in this case is +0.64V to +2.73V nominal.
b. Tie V
RB
to AGND, and tie V
RT
to V
RTS
respectively. The
analog input voltage range is 0 to +2.39V in this case.
FUNCTIONAL SPECIFICATIONS
(Specification are typical at T
A
= +25°C, +V
RT
= +2.5V, V
RB
= +0.5V, +AV
S
= +DV
S
=
+5v, f
S
= 20MHz sampling unless otherwise specified.)
ANALOG INPUTS
MIN.
TYP.
MAX.
UNITS
Input Voltage Range
(V
IN
)
Input Capacitance
(V
IN
= 1.5Vdc+0.07V
RMS
)
Input Impedance
Input Signal Bandwidth
(V
IN
-2Vp-p, –1dB)
—
—
+0.5 to +2.5
11
—
—
Volts
pF
—
—
12.5
18
—
—
k
MHz
REFERENCE INPUTS
Ref. Resitance
Ref. Current
Ref. Voltage
V
RT
to V
RB
230
4.5
+1.8
0
–10
0
+0.6
+1.96
+2.25
300
6.6
—
—
–35
+15
+0.64
+2.09
+2.39
450
8.7
+2.8
V
RT
–60
+45
+0.68
+2.21
+2.53
mA
Volts
Volts
mV
mV
Volts
Volts
Volts
V
RT
V
RB
V
RT
V
RB
Offset Voltage
Self Bias I
V
RBS
V
RTS
-V
RBS
Self Bias II
V
RTS
DIGITAL INPUTS
Input Voltage
(CMOS)
Logic Levels (V
IH
) "1"
Logic Level (V
IL
) "0"
Input Current
(@V
IH
=+DV
S
)"1"
(@V
IL
=0) "0"
Clock Pulse Width
T
PW1
(A/D CLK)
+4
—
—
—
25
25
—
—
—
—
—
—
—
+1
5
5
—
—
Volts
Volts
μA
μA
ns
ns
T
PW0
DIGITAL OUTPUTS
Output Data
Output Voltage
Output Current
Logic Level "1"
Logic Level "0"
Output Current
Logic Level "1"
Logic Level "0"
Output Data Delay,
Td
8-bit Binary Parallel
3-State TTL compatible
–1.1
+3.7
—
—
—
—
mA
mA
—
—
—
—
—
18
16
16
30
μA
μA
ns
PERFORMANCE
Resolution
Maximum Sampling Rate
Minimum Sampling Rate
Aperature Delay,
T
A
Aperature Jitter
Differential Linearity Error
Integral Linearity Error
Differential Gain Error
Differential Phase Error
8
20
—
—
—
—
—
—
—
—
—
—
4
30
±0.3
+0.5
1
0.5
—
—
0.5
—
—
±0.5
+1.3
—
—
Bit
MHz
MHz
ns
ps
LSB
LSB
%
deg
POWER REQUIREMENTS
MIN.
TYP.
MAX.
UNITS
Power Supply
(+AV
S
, +DV
S
)
I A GND - D GND I
Power Supply Current
Power Dissipation
+4.75
—
—
—
+5.0
—
12
60
+5.25
100
17
85
Volts
mV
mA
mW
PHYSICAL/ENVIRONMENTAL
Operating Temp. Range
Storage Temp. Range
Package Type
–40 to +85°C
–55 to +150°C
24-pin Plastic DIP
24-pin Plastic SOP
2.0 grams
0.3 grams
ADC-305-1
ADC-305-3
ADC-305-1
ADC-305-3
Weight
Footnotes:
See Technical Note 4
Short V
RB
(pin 23) to V
RBS
(pin 22).
Short V
RT
(pin 17) to V
RTS
(pin 16).
Short V
RB
(pin 23) to A GND.
Short V
RT
(pin 17) to V
RTS
(pin 16).
2
OE=OV, V
OH
=+DV
S
–0.5V,
V
OL
=+0.4V
OE=+DV
S
, V
OH
=+DV
S
, V
OL
=0V
NTSC 40IRE mode ramp, 14.3MHz
sampling
Table 1. Digital Output Coding
PARAMETERS
MIN
MAX
UNITS
Power Supply Voltage
(+AV
S
, +DV
S
)
Analog Input Voltage
(V
IN
)
Reference Input Voltage
(V
RT
, V
RB
)
Digital Input Voltage
(V
IH
, V
IL
)
Digital Output Voltage
(V
OH
, V
OL
)
–0.5
–0.5
–0.5
–0.5
–0.5
+7
Volts
Volts
Volts
Volts
Volts
+AV
S
+0.5
+AV
S
+0.5
+DV
S
+0.5
+DV
S
+0.5
ABSOLUTE MAXIMUM RATINGS (T
A
= 25°C)
STEP
DATA BITS OUT
MSB
V
IN
CODE
DEC
HEX
LSB
O
V
Zero
0
00
0 0 0 0
0 0 0 0
+0.9922V
+1.000V
+1/2FS –1LSB
+1/2FS
127
128
7F
80
0 1 1 1
1 0 0 0
1 1 1 1
0 0 0 0
+1.9922V
+FS
255
FF
1 1 1 1
1 1 1 1
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