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參數(shù)資料
| 型號： | ADAV400 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | 音頻編解碼器與嵌入式的SigmaDSP處理器 |
| 文件頁數(shù)： | 28/36頁 |
| 文件大?。?/td> | 446K |
| 代理商： | ADAV400 |
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ADAV400
CONTROL REGISTERS
Table 28. Audio Register Map
Register Address (Hex)
0x1052
0x1053
0x1054
0x1055
0x1056
0x1057
0x1058
0x1059
0x105A
0x110D
0x1113
Rev. 0 | Page 28 of 36
Register Name
Audio core control register (see Table 29)
RAM modulo control register (see Table 30)
Serial output control register (see Table 31)
Serial input control register (see Table 32)
SRC serial port control register (see Table 33)
ADC input mux control register (see Table 34)
Power control register (see Table 35)
User Control Register 1 (see Table 37)
User Control Register 2 (see Table 36)
DAC amplifier register (see Table 38)
Headphone amplifier register (see Table 39)
Register Width (Bits)
16
8
16
8
8
16
16
16
16
16
16
Table 29. Audio Core Control Register
Register Address 0x1052 Default Readback = 0x4000
Register Bits
Function
15
Reserved (set to 0)
14
1
Enable SDO2 and SDO3
0 = enabled
1 = disabled
13
Indicates when slew RAM is muted (read only)
12
Equivalent to writing 0s to the target RAM
0 = normal operation
1 = RAM zeroed
11
Reserved (set to 0)
10
Reserved (set to 0)
9
Clears internal processor registers (active low)
0 = registers cleared
1 = normal operation
8
Forces multiplier input to 0
0 = normal operation
1 = forced to 0
7
Initializes data RAM to zero
0 = normal operation
1 = enabled
Register Bits
6
5
4
3:2
1:0
Function
Mutes serial input ports
0 = normal operation
1 = muted
Initiates safeload-to-target/slew RAM
0 = off
1 = on
Initiates safeload-to-parameter RAM
0 = off
1 = on
Reserved (set to 0)
Programs length
00 = 2560 (48 kHz)
01 = 1280 (96 kHz digital IO only)
10 = 640 (192 kHz digital IO only)
11 = reserved
1
The polarity of this bit is inverted when read.
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