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參數(shù)資料
| 型號： | ADAV400 |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | Codec |
| 英文描述： | Audio Codec with Embedded SigmaDSP Processor |
| 中文描述： | 音頻編解碼器與嵌入式的SigmaDSP處理器 |
| 文件頁數(shù)： | 10/36頁 |
| 文件大小： | 446K |
| 代理商： | ADAV400 |
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ADAV400
Pin No.
33
Rev. 0 | Page 10 of 36
Mnemonic
MCLKI
I/O
I
Description
Master Clock Input. The ADAV400 uses a phase-locked loop (PLL) to generate all of the appropriate
internal clock for the DSP core.
Audio Clock Output. The MCLKO pin can be programmed to output the internal audio clock.
Bit Clock for Serial Data Input/Output. This clock and the LRCLK1 are used as clock and frame sync signals
for the SDINx and SDOx pins. These clocks are inputs to the ADAV400 when the port is configured as a
slave, and outputs when the port is configured as a master. On power up, these pins are set to slave mode
to avoid conflicts with external master mode devices.
Left/Right Clock for Serial Data Input/Output. This clock and the BCLK1 are used as clock and frame sync
signals for the SDINx and SDOx pins.
Serial Data Outputs.
34
35
MCLKO
BCLK1
O
I/O
36
LRCLK1
I/O
37, 38,
42, 43
39, 44,
45
46
49
50
SDO [0:3]
0
NC
These pins should be left unconnected.
RESET
AVDD2
PLL_LF
I
Active Low Reset Signal. After RESET the ADAV400 is powered down.
Analog Power Supply Pin for the PLL. Connect this pin to 3.3 V and decouple to AGND (Pin 51).
PLL Loop Filter. External components are required to allow the PLL to function correctly. See the PLL
Block section for details of these components.
PLL Ground. Connect this pin to the analog ground plane.
Headphone Driver Ground. Connect this pin to the analog ground plane.
Left Headphone Output. Analog output from the headphone amplifiers.
Right Headphone Output. Analog output from the headphone amplifiers.
Analog Power Supply Pin for the headphone amplifier. Connect this pin to 3.3 V and decouple to AGND
(Pin 52).
Auxiliary Analog Output Left 1
Auxiliary Analog Output Right 1.
Main Analog Output 1 to Output 4.
Auxiliary Analog Output Left 2.
Auxiliary Analog Output Right 2.
Test Pin. This pin should be left unconnected.
DAC Filter Decoupling Node. Decouple this pin to AGND (Pin 69).
Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 69).
DAC Ground. Connect this pin to the analog ground plane.
Analog Power Supply Pin for the DAC. Connect this pin to 3.3 V and decouple to AGND (Pin 70).
Left Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor for
2 V rms input, as shown in Figure 17.
Right Analog Input 1 to Input 4. The analog inputs are current inputs typically driven via a 20 kΩ resistor
for 2 V rms input, as shown in Figure 17.
DAC External Bias Resistor. This is an external bias pin for the DAC circuitry. Connect a 20 kΩ resistor
between this pin and AGND.
51
52
53
54
55
AGND
AGND
HPOUTL
HPOUTR
AVDD3
O
O
56
57
58 to 61
62
63
64
67
68
69, 70
71
72, 74,
76, 78
73, 75,
77, 79
80
AUXL1
AUXR1
VOUT [1:4]
AUXL2
AUXR2
TEST2
FILTD
AVDD4
AGND
AVDD5
AINL [1:4]
O
O
O
O
O
I
AINR [1:4]
I
IDAC
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