參數(shù)資料
型號(hào)： ADAU1781BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 42/92頁(yè)
文件大?。?/td> 0K
描述： IC SIGMADSP CODEC LN 32LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 立體聲音頻
數(shù)據(jù)接口： I²C，串行，SPI?
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
S/N 比，標(biāo)準(zhǔn) ADC / DAC (db)： 100 / 105（差分），100 / 103（單端）
動(dòng)態(tài)范圍，標(biāo)準(zhǔn) ADC / DAC (db)： 99.2 / 105（差分），99.2 / 103（單端）
電壓 - 電源，模擬： 1.8 V ~ 3.65 V
電壓 - 電源，數(shù)字： 1.63 V ~ 3.65 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤
ADAU1781
Rev. B| Page 47 of 92
APPLICATIONS INFORMATION
POWER SUPPLY BYPASS CAPACITORS
Each analog and digital power supply pin should be bypassed to
its nearest appropriate ground pin with a single 100 nF capacitor.
The connections to each side of the capacitor should be as short
as possible, and the trace should stay on a single layer with no
vias. For maximum effectiveness, locate the capacitor equidistant
from the power and ground pins or, when equidistant placement
is not possible, slightly closer to the power pin. Thermal connec-
tions to the ground planes should be made on the far side of the
capacitor.
Each supply signal on the board should also be bypassed with a
single bulk capacitor (10 μF to 47 μF).
VDD
GND
TO GND
TO VDD
CAPACITOR
08314-
051
Figure 55. Recommended Power Supply Bypass Capacitor Layout
GSM NOISE FILTER
In mobile applications, excessive 217 Hz GSM noise on the
analog supply pins can degrade the quality of the audio signal.
To avoid this problem, it is recommended that an LC filter be
used in series with the bypass capacitors for the AVDD pins.
This filter should consist of a 1.2 nH inductor and a 9.1 pF
capacitor in series between AVDDx and ground, as shown in
AVDD1
AVDD2
0.1F
9.1pF
1.2nH
10F
+
08314-
052
Figure 56. GSM Filter on the Analog Supply Pins
GROUNDING
A single ground plane should be used in the application layout.
Components in an analog signal path should be placed away
from digital signals.
SPEAKER DRIVER SUPPLY TRACE (AVDD2)
The trace supplying power to the AVDD2 pin has higher current
requirements than the AVDD1 pin (up to 300 mA). An appro-
priately thick trace is recommended.
EXPOSED PAD PCB DESIGN
The ADAU1781 LFCSP package has an exposed pad on the
underside. This pad is used to couple the package to the PCB
for heat dissipation when using the outputs to drive earpiece or
headphone loads. When designing a board for the ADAU1781,
special consideration should be given to the following:
A copper layer equal in size to the exposed pad should be
on all layers of the board, from top to bottom, and should
connect somewhere to a dedicated copper board layer (see
Vias should be placed to connect all layers of copper,
allowing for efficient heat and energy conductivity. For an
example, see Figure 58, which has nine vias arranged in a
3 inch × 3 inch grid in the pad area.
TOP
POWER
GROUND
BOTTOM
COPPER SQUARES
VIAS
08314-
053
Figure 57. Exposed Pad Layout Example, Side View
08314-
054
Figure 58. Exposed Pad Layout Example, Top View
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