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參數(shù)資料
| 型號： | ADAU1701JSTZ-RL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48 |
| 文件頁數(shù)： | 32/43頁 |
| 文件大小： | 625K |
| 代理商： | ADAU1701JSTZ-RL |
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ADAU1701
Preliminary Technical Data
Rev. PrF | Page 32 of 43
Aux ADC
Input Pin
20 kΩ
10 kΩ
S1
S2
1.8 pF
Figure 31. Auxiliary ADC input circuit
Figure 31 shows the input circuit for the auxiliary ADC. Switch
S1 enables the aux ADC, and is set by bit 15 of the Aux ADC
enable register. The sampling switch, S2, operates at the audio
sampling frequency (fs), which is 48 kHz with a 12.288 MHz
crystal connected to the chip’s oscillator.
The aux ADC registers can be written to directly after bit 8 in
the DSP core control register has been set. In this mode, the
voltages on the analog inputs are not written into the registers,
but rather the data in the registers is written from the control
port. These registers take a single byte of data when in control
port write mode.
PVDD supplies the 3.3 V power for the aux ADC’s analog input.
The digital core of the aux ADC is powered with the 1.8 V
DVDD signal.
Table 40. Multi-Purpose Pin Aux ADC Mapping
Multipurpose Pin
Function
MP0
N/A
MP1
N/A
MP2
ADC1
MP3
ADC2
MP4
N/A
MP5
N/A
MP6
N/A
MP7
N/A
MP8
ADC3
MP9
ADC0
MP10
N/A
MP11
N/A
Table 41. Auxiliary ADC & Power Control Register (2082)
Register Bits
Function
15:10
Reserved, set to 0
9:8
Aux ADC Filtering
00 = 4-bit hysteresis (12 bit level)
01 = 5-bit hysteresis (12 bit level)
01 = Hysteresis bypassed
11 = Low-pass filter bypassed
7
ADC power-down (both ADCs)
6
Voltage reference buffer power-down
5
Voltage reference power-down
4
Reserved, set to 0
3
DAC0 power-down
2
DAC1 power-down
1
0
Table 42. Aux ADC Enable Register (2084)
Register Bits
Function
15
Enable Auxiliary ADC
14:0
Reserved, set to 0
GENERAL PURPOSE INPUT/OUTPUTS
The general purpose input/output (GPIO) pins can be used as
either inputs or outputs. These pins are readable and settable
either through the control interface or directly by the SigmaDSP
core. When set as inputs, they can be used with push-button
switches or rotary encoders to control DSP program settings.
Digital outputs may be used to drive LEDs or external logic to
indicate the status of internal signals and control other devices.
Examples of this use include indicating signal overload, signal
present, and button press confirmation.
DAC2 power-down
DAC3 power-down
When set as outputs, these pins can typically drive 5 mA. This is
enough current to directly drive high-efficiency LEDs, which
typically need 2-4 mA. Standard LEDs require about 20 mA and
can be driven from a GPIO output with an external transistor or
buffer. When the GPIO pins are set as open-collector outputs,
they should be pulled up to a maximum voltage of 3.3 V (the
voltage on IOVDD).
SERIAL DATA INPUT/OUTPUT PORTS
The ADAU1701’s flexible serial data input and output ports can
be set to accept or transmit data in 2-channel formats or in an
8-channel TDM stream. Data is processed in twos complement,
MSB-first format. The left channel data field always precedes
the right channel data field in the 2-channel streams. In the
TDM modes, slots 0 to 3 fall in the first half of the audio frame,
and slots 4 to 7 are in the second half of the frame. TDM mode
allows fewer multipurpose pins to be used, freeing more pins
for other functions. The serial modes are set in the serial output
and serial input control registers.
The serial data clocks need to be synchronous with the
ADAU1701’s master clock input.
The input control register allows control of clock polarity and
data input modes. The valid data formats are I
2
S , left-justified,
right-justified (24-, 20-, 18-, or 16-bit), and 8-channel TDM. In
all modes except for the right-justified modes, the serial port
will accept an arbitrary number of bits up to a limit of 24. Extra
bits will not cause an error, but they will be truncated internally.
Proper operation of the right-justified modes requires that there
be exactly 64 BCLKs per audio frame. The TDM data is input
on SDATA_IN0. The LRCLK in TDM mode can be input to the
ADAU1701 either as a 50/50 duty cycle clock or as a bit-wide
pulse.
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| ADAU1702JSTZ | 功能描述:IC AUDIO PROC 2ADC/4DAC 48-LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6 |
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