參數(shù)資料
型號(hào)： ADAU1701JSTZ-RL
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： SigmaDSP 28/56-Bit Audio Processor with 2ADC/4DAC
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP48
封裝： ROHS COMPLIANT, PLASTIC, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 21/43頁(yè)
文件大?。?/td> 625K
代理商： ADAU1701JSTZ-RL
Preliminary Technical Data
ADAU1701
Subaddress
The 12-bit Subaddress word is decoded into a location in one of
the memories or registers. This subaddress is the location of the
appropriate RAM location or register.
Rev. PrF | Page 21 of 43
Data Bytes
The number of data bytes varies according to the register or
memory being accessed. In burst write mode, an initial
subaddress is given followed by a continuous sequence of data
for consecutive memory/register locations. The detailed data
format diagram for continuous-mode operation is given in the
Control Port Read/Write Data Formats section.
A sample timing diagram for a single SPI write operation to the
parameter RAM is shown in Figure 28. A sample timing
diagram of a single SPI read operation is shown in Figure 29.
The COUT pin goes from three-state to driven at the beginning
of Byte 3. In this example, Bytes 0 to 2 contain the addresses and
R/W bit, and subsequent bytes carry the data.
R/W
0
SCK
SDA
0
0
0
ADR
SEL
ACK. BY
ADAU1701
FRAME 2
SUBADDRESS BYTE 1
START BY
MASTER
ACK. BY
ADAU1701
STOP BY
MASTER
SDA
(CONTINUED)
FRAME 3
DATA BYTE 1
ACK. BY
ADAU1701
FRAME 2
SUBADDRESS BYTE 2
SCK
(CONTINUED)
FRAME 1
CHIP ADDRESS BYTE
ACK. BY
ADAU1701
0
0
Figure 22. ADAU1701 I2C Write Clocking
R/W
SCK
SDA
ADR
SEL
ACK. BY
ADAU1701
FRAME 2
SUBADDRESS BYTE 1
START BY
MASTER
SCK
(CONTINUED)
SDA
(CONTINUED)
FRAME 1
CHIP ADDRESS BYTE
ACK. BY
ADAU1701
R/W
ADR
SEL
ACK. BY
ADAU1701
REPEATED
START BY
MASTER
ACK. BY
ADAU1701
FRAME 3
SUBADDRESS BYTE 2
FRAME 4
CHIP ADDRESS BYTE
SCK
(CONTINUED)
SDA
(CONTINUED)
ACK. BY
MASTER
STOP BY
MASTER
FRAME 6
READ DATA BYTE 2
ACK. BY
MASTER
FRAME 5
READ DATA BYTE 1
Figure 23. ADAU1701 I
2
C Read Clocking
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