- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄10218 > ADAU1461WBCPZ-RL (Analog Devices Inc)IC SIGMADSP 24BIT 96KHZ PLL 32 PDF資料下載
參數(shù)資料
| 型號(hào)： | ADAU1461WBCPZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 35/88頁 |
| 文件大小： | 0K |
| 描述： | IC SIGMADSP 24BIT 96KHZ PLL 32 |
| 標(biāo)準(zhǔn)包裝： | 5,000 |
| 系列： | SigmaDSP® |
| 類型： | 音頻處理器 |
| 應(yīng)用： | 車載音頻 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-VFQFN 裸露焊盤，CSP |
| 供應(yīng)商設(shè)備封裝： | 32-LFCSP-VQ |
| 包裝： | 帶卷 (TR) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁
ADAU1461
Rev. 0 | Page 40 of 88
SERIAL DATA INPUT/OUTPUT PORTS
The flexible serial data input and output ports of the ADAU1461
can be set to accept or transmit data in 2-channel format or in
a 4-channel or 8-channel TDM stream to interface to external
ADCs or DACs. Data is processed in twos complement, MSB
first format. The left channel data field always precedes the right
channel data field in 2-channel streams. In TDM mode, Slot 0
to Slot 3 are in the first half of the audio frame, and Slot 4 to
Slot 7 are in the second half of the frame. The serial modes and
the position of the data in the frame are set in Register R15 to
Register R18 (serial port and converter control registers,
Address 0x4015 to Address 0x4018).
If the PLL of the ADAU1461 is not used, the serial data clocks
must be synchronous with the ADAU1461 master clock input.
The LRCLK and BCLK pins are used to clock both the serial
input and output ports. The ADAU1461 can be set as the master
or the slave in a system. Because there is only one set of serial
data clocks, the input and output ports must always be both
master or both slave.
Register R15 and Register R16 (serial port control registers,
Address 0x4015 and Address 0x4016) allow control of clock
polarity and data input modes. The valid data formats are I2S,
left-justified, right-justified (24-/20-/18-/16-bit), and TDM. In
all modes except for the right-justified modes, the serial port
inputs an arbitrary number of bits up to a limit of 24. Extra bits
do not cause an error, but they are truncated internally.
The serial port can operate with an arbitrary number of BCLK
transitions in each LRCLK frame. The LRCLK in TDM mode
can be input to the ADAU1461 either as a 50% duty cycle clock
or as a bit-wide pulse.
When the LRCLK is set as a pulse, a 47 pF capacitor should be
connected between the LRCLK pin and ground (see Figure 57).
This capacitor is necessary in both master and slave modes to
properly align the LRCLK signal to the serial data stream.
LRCLK
ADAU1461
BCLK
08
914
-07
1
47pF
Figure 57. LRCLK Capacitor Alignment, TDM Pulse Mode
In TDM 8 mode, the ADAU1461 can be a master for fS up to
48 kHz. Table 23 lists the modes in which the serial output port
can function.
Table 23. Serial Output Port Master/Slave Mode Capabilities
fS
2-Channel Modes (I2S, Left-
Justified, Right-Justified)
8-Channel TDM
48 kHz
Master and slave
96 kHz
Master and slave
Slave
Table 24 describes the proper configurations for standard audio
data formats.
Table 24. Data Format Configurations
Format
LRCLK Polarity (LRPOL)
LRCLK Mode
(LRMOD)
BCLK Polarity
(BPOL)
BCLK Cycles/Audio
Frame (BPF[2:0])
Data Delay from LRCLK
Edge (LRDEL[1:0])
I2S
(see Figure 58)
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 1 BCLK
Left-Justified (see
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
32 to 64
Aligned with LRCLK edge
Right-Justified
(see Figure 60)
Frame begins on rising edge
50% duty cycle
Data changes
on falling edge
32 to 64
Delayed from LRCLK edge
by 8 or 16 BCLKs
TDM with Clock
(see Figure 61)
Frame begins on falling edge
50% duty cycle
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
TDM with Pulse
(see Figure 62)
Frame begins on rising edge
Pulse
Data changes
on falling edge
64 to 256
Delayed from start of word
clock by 1 BCLK
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SP3222EBCA-L/TR | IC TXRX RS232 ESD TRUE 20SSOP |
| AD7657BSTZ-REEL | IC ADC 14BIT 6CH 250KSPS 64-LQFP |
| LTC1867AIGN | IC ADC 16BIT 8CH 200KSPS 16SSOP |
| SP211EHCT-L/TR | IC TXRX RS232 MULTI-CH 28SOIC |
| CS44800-CQZR | IC AMP CTLR DGTL 8CH 64-LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADAU1462WBCPZ150 | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:管件 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:1 |
| ADAU1462WBCPZ150RL | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:2,000 |
| ADAU1462WBCPZ300 | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:管件 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:1 |
| ADAU1462WBCPZ300RL | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:帶卷（TR） 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:2,000 |
| ADAU1463WBCPZ150 | 功能描述:32BIT SIGMADSP AUDIO 16K/48K 制造商:analog devices inc. 系列:* 包裝:管件 零件狀態(tài):在售 安裝類型:表面貼裝 封裝/外殼:72-VFQFN 裸露焊盤，CSP 供應(yīng)商器件封裝:72-LFCSP（10x10） 標(biāo)準(zhǔn)包裝:1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。