參數(shù)資料
型號： ADAU1401YSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 35/52頁
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標準包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應商設備封裝： 48-LQFP（7x7）
包裝： 托盤
ADAU1401
Data Sheet
Rev. C | Page 40 of 52
2076 (0x081C)—DSP CORE CONTROL REGISTER
Table 46. DSP Core Control Register Bit Map
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Default
RSVD
GD1
GD0
RSVD
AACW
GPCW
IFCW
IST
ADM
DAM
CR
SR1
SR0
0x0000
Table 47. DSP Core Control Register
Bit Name
Description
GPIO Debounce Control. Sets debounce time of multipurpose pins that are set as GPIO inputs.
GD[1:0]
Time (ms)
00
20
01
40
10
GD[1:0]
11
5
AACW
Auxiliary ADC Data Registers Control Port Write Mode. Setting this bit allows data to be written directly to the
auxiliary ADC data registers (2057 to 2060) from the control port. When this bit is set, the auxiliary ADC data
registers ignore the settings on the multipurpose pins.
GPCW
GPIO Pin Setting Register Control Port Write Mode. When this bit is set, the GPIO pin setting register (2056) can
be written to directly from the control port and this register ignores the input settings on the multipurpose
pins.
IFCW
Interface Registers Control Port Write Mode. When this bit is set, data can be written directly to the interface
registers (2048 to 2055) from the control port. In that state, the interface registers are not written from the
SigmaDSP program.
IST
Initiate Safeload Transfer. Setting this bit to 1 initiates a safeload transfer to the parameter RAM. This bit is
automatically cleared when the operation is complete. There are five safeload register pairs (address/data);
only those registers that have been written since the last safeload event are transferred to the parameter RAM.
ADM
Mute ADCs. This bit mutes the output of the ADCs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the ADCs.
DAM
Mute DACs. This bit mutes the output of the DACs. The bit defaults to 0 and is active low; therefore, it must be
set to 1 to transmit audio signals from the DACs.
CR
Clear Internal Registers to 0. This bit defaults to 0 and is active low. It must be set to 1 for a signal to pass
through the SigmaDSP core.
SR[1:0]
Sample Rate. These bits set the number of DSP instructions for every sample and the sample rate at which the
ADAU1401 operates. At the default setting of 1×, there are 1024 instructions per audio sample. This setting
should be used with sample rates such as 48 kHz and 44.1 kHz.
At the 2× setting, the number of instructions per frame is halved to 512 and the ADCs and DACs nominally run
at a 96 kHz sample rate.
At the 4× setting, there are 256 instructions per cycle and the converters run at a 192 kHz sample rate.
SR[1:0]
Setting
00
1× (1024 instructions)
01
2× (512 instructions)
10
4× (256 instructions)
11
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ADAU1401YSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1421YSTZ 制造商:Analog Devices 功能描述:
ADAU1421YSTZ-REEL 制造商:Analog Devices 功能描述:
ADAU1442 制造商:AD 制造商全稱:Analog Devices 功能描述:SigmaDSP Digital Audio Processor
ADAU1442YSVZ-3A 功能描述:IC SIGMADSP 28B 175MHZ 100TQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應商設備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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