參數(shù)資料
型號(hào)： ADAU1361BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 17/80頁(yè)
文件大?。?/td> 0K
描述： IC CODEC 24B PLL 32LFCSP
標(biāo)準(zhǔn)包裝： 1
類型： 音頻編解碼器
數(shù)據(jù)接口： 串行
分辨率（位）： 24 b
ADC / DAC 數(shù)量： 2 / 2
三角積分調(diào)變： 無(wú)
電壓 - 電源，模擬： 1.8 V ~ 3.6 V
電壓 - 電源，數(shù)字： 1.8 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 32-LFCSP-VQ
包裝： 托盤
產(chǎn)品目錄頁(yè)面： 776 (CN2011-ZH PDF)
ADAU1361
Rev. C | Page 24 of 80
STARTUP, INITIALIZATION, AND POWER
This section describes the procedure for properly starting up
the ADAU1361. The following sequence provides a high level
approach to the proper initiation of the system.
1.
Apply power to the ADAU1361.
2.
Lock the PLL to the input clock (if using the PLL).
3.
Enable the core clock.
4.
Load the register settings.
POWER-UP SEQUENCE
The ADAU1361 uses a power-on reset (POR) circuit to
reset the registers upon power-up. The POR monitors the
DVDDOUT pin and generates a reset signal whenever power
is applied to the chip. During the reset, the ADAU1361 is set
to the default values documented in the register map (see the
Control Registers section). Typically, with a 10 μF capacitor on
AVDD, the POR takes approximately 14 ms.
07
67
9-
07
4
AVDD
POR
PART READY
POR
ACTIVE
POR ACTIVE
DVDDOUT
1.35V
0.95V
1.5V
POR
FINISHED
Figure 28. Power-On Reset Sequence
The PLL lock time is dependent on the MCLK rate. Typical
lock times are provided in Table 11.
Table 11. PLL Lock Times
PLL Mode
MCLK Frequency
Lock Time (Typical)
Fractional
8 MHz
3.5 ms
Fractional
12 MHz
3.0 ms
Integer
12.288 MHz
2.96 ms
Fractional
13 MHz
2.4 ms
Fractional
14.4 MHz
2.4 ms
Fractional
19.2 MHz
2.98 ms
Fractional
19.68 MHz
2.98 ms
Fractional
19.8 MHz
2.98 ms
Fractional
24 MHz
2.95 ms
Integer
24.576 MHz
2.96 ms
Fractional
26 MHz
2.4 ms
Fractional
27 MHz
2.4 ms
POWER REDUCTION MODES
Sections of the ADAU1361 chip can be turned on and off as
needed to reduce power consumption. These include the ADCs,
the DACs, and the PLL.
In addition, the control registers can be used to configure some
functions for power saving, normal, or enhanced performance
operation. See the Control Registers section for more
information.
The digital filters of the ADCs and DACs can each be set to over-
sampling ratios of 64× or 128× (default). Setting the oversampling
ratios to 64× for these filters lowers power consumption with a
minimal impact on performance. See the Digital Filters section
for specifications; see the Typical Performance Characteristics
section for graphs of these filters.
DIGITAL POWER SUPPLY
The digital power supply for the ADAU1361 is generated from
an internal regulator. This regulator generates a 1.5 V supply
internally. The only external connection to this regulator is the
DVDDOUT bypassing point. A 100 nF capacitor and a 10 μF
capacitor should be connected between this pin and DGND.
INPUT/OUTPUT POWER SUPPLY
The power for the digital output pins is supplied from IOVDD,
and this pin also sets the highest input voltage that should be
seen on the digital input pins. IOVDD should be set between
1.8 V and 3.3 V; no digital input signal should be at a voltage
level higher than the one on IOVDD. The current draw of this
pin is variable because it depends on the loads of the digital
outputs. IOVDD should be decoupled to DGND with a 100 nF
capacitor and a 10 μF capacitor.
CLOCK GENERATION AND MANAGEMENT
The ADAU1361 uses a flexible clocking scheme that enables the
use of many different input clock rates. The PLL can be bypassed
or used, resulting in two different approaches to clock manage-
ment. For more information about clocking schemes, PLL
configuration, and sampling rates, see the Clocking and
Case 1: PLL Is Bypassed
If the PLL is bypassed, the core clock is derived directly from
the MCLK input. The rate of this clock must be set properly in
Register R0 (clock control register, Address 0x4000) using the
INFREQ[1:0] bits. When the PLL is bypassed, supported external
clock rates are 256 × fS, 512 × fS, 768 × fS, and 1024 × fS, where fS
is the base sampling rate. The core clock of the chip is off until
the core clock enable bit (COREN) is asserted.
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