參數(shù)資料
型號(hào)： ADATE207BBPZ
廠商： Analog Devices Inc
文件頁數(shù)： 6/36頁
文件大?。?/td> 0K
描述： IC TIMING FORMATTER QUAD 256BGA
標(biāo)準(zhǔn)包裝： 1
類型： 四針定時(shí)格式器
PLL： 是
主要目的： 自動(dòng)測(cè)試設(shè)備
電路數(shù)： 4
頻率 - 最大： 100MHz
電源電壓： 2.375 V ~ 2.625 V
工作溫度： -25°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 256-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 256-BGA（27x27）
包裝： 托盤
ADATE207
Rev. 0 | Page 14 of 36
T0
M
C
M
T0
M
INPUT_DELAY
C
44
11
C
11
PROGRAMMABLE
RTD DELAY [0:31]
C
1
C
DUT
C
FIFO
2
T0
PROGRAMMABLE
T0 DELAY [0:30]
T0
3
PAT_PATDATA
FAIL
DUTDATA
LEGEND
1
RTD COMPENSATION
CLK400
PIPELINE
REGISTER
MCLK
PIPELINE
REGISTER
T0
PIPELINE
REGISTER
05
55
7-
0
02
Figure 8. Pipeline Diagram
Dual comparator inputs of the even channels (0 and 2) are
routed to the compare logic of adjacent channels to provide
×2 multiplexing. In ×2 multiplexing, Pin 0 and Pin 2 comparator
inputs route to Pin 1 and Pin 3, respectively, providing up to
eight compare events per cycle on the multiplexed channels.
PIPELINE CONSIDERATIONS
For proper functionality, drive actions, compare events, and fail
accumulation mask requirements need to be coordinated within
the device by adjusting the internal delay paths. The ADATE207
provides two programmable delay paths, the RTD pipeline and
the T0 alignment pipeline, as shown in Figure 8. The pattern
input and output signals are synchronous with the MCLK and
pipelined on T0 periods.
Figure 8 shows the pipeline diagram of the ADATE207. The T0
delay pipeline is programmable. It must be sufficiently deep to
cover the round trip delay compensation, yet no deeper than
the FIFO depth of the fail logic.
The minimum T0 alignment pipeline depth needed is
dependent on the programmed RTD compensation. The
programmed T0 alignment pipeline depth must conform to the
values listed in Table 10. The maximum number of 30 can be
used in any circumstance. Depending upon the MCLK rate and
the programmed RTD compensation, a smaller pipeline depth
can be used.
Table 10. T0 Pipeline Requirements
T0 Alignment Pipelines
Minimum
Maximum
10.5 + RTD/4
30
MCLK
Q
D
CE
T0 PIPELINE
PER_EARLY_T0EN
PER_EARLY_C0EN
PAT_PATDATA_x[7:0]
PAT_DATA_VALID
PAT_MASK[3:0]
INPUT_DELAY[7:0]
05
557
-02
0
Figure 9. PER_EARLY_T0EN Pipelining
Figure 9 shows the pipelining of PER_EARLY_T0EN (the
period start signal). It is pipelined with MCLK to control the T0
pipelines within the chip. It uses two MCLK pipelines within
the chip to distribute the PER_EARLY_T0EN signal to all of the
T0 pipeline registers.
PER_EARLY_T0EN and PER_EARLY_C0EN, the period start
signals, and the global INPUT_DELAY signals are pipelined
into the ADATE207 with different depths. The PER_EARLY_T0EN
and PER_EARLY_C0EN are pipelined with two MCLK pipelines
prior to the enable pins of the T0 clocked pipelines. The
INPUT_DELAY signals are not pipelined on T0 clock pipelines,
but have only two MCLK pipelines prior to use by the timing
generators.
Figure 10 shows the relative pipelines for INPUT_DELAY and
the period enables.
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