參數(shù)資料
型號(hào)： ADATE206BSV
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： 500 MHz Dual DCL
中文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封裝： MS-026-AED-HD, TQFP-100
文件頁(yè)數(shù)： 15/16頁(yè)
文件大小： 246K
代理商： ADATE206BSV
ADATE206
THEORY OF OPERATION
The ADATE206 has two general classes of logic inputs:
differential inputs for controlling functions that generally need
to be operated at high speed, and single-ended CMOS inputs
for setting operating modes or other low speed functions. The
differential inputs have a wide common-mode range that allows
them to be used with a variety of logic families. The differential
inputs can be used single-ended, with one input from each pair
of inputs tied to a fixed reference. However, this makes precise
timing more difficult to achieve.
Rev. 0 | Page 15 of 16
These differential input pins provide 50 Ω input termination
resistors for use as desired. The single-ended inputs have an
input range compatible with most logic families and are high
impedance to make driving them very easy. The switching
threshold for the single-ended inputs is preset to one-half of the
voltage at the CMOS_VDD pin.
Table 4. Driver and Load Modes
LDEN
(CMOS Single-Ended)
0
0
0
0
0
0
1
1
1
VTEN
(CMOS Single-Ended)
DR_EN
(High Speed Differential)
DR_DATA
(High Speed Differential)
Driver
Status
Load
Status
0
0
0
1
1
1
0
0
0
0
1
1
0
1
1
0
1
1
X
0
1
X
0
1
X
0
1
High-Z
VIL
VIH
VIT
VIL
VIH
High-Z
VIL
VIH
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
ON
High-Z
High-Z
Table 5. Comparator Low Leakage Mode
CLLM
(CMOS Single-Ended)
Typical DUT Pin Bias Current
0
1
1 μA
10 nA
Table 6. Rise/Fall Time Selection 3 V, 10% to 90%, Unterminated
Slew1
Slew0
0
0
0
1
1
0
1
1
Tr/Tf (ns)
0.7
0.95
1.4
2.8
Table 7. Comparator Logic Function
DUT Pin Voltage
>CVL
>CVH
>CVL
<CVH
<CVL
>CVH
<CVL
<CVH
Output States
COMP_L_P
1
1
0
0
COMP_L_N
0
0
1
1
COMP_H_P
1
0
1
0
COMP_H_N
0
1
0
1
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