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參數(shù)資料
| 型號： | ADADC80-Z-12 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT INTEGRATED 32-CDIP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 40k |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 800mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -25°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 32-CDIP（0.910"，23.12mm） |
| 供應(yīng)商設(shè)備封裝： | 32-CDIP 側(cè)面銅焊 |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 2 個單端，單極；2 個單端，雙極 |
ADADC80
Rev. E | Page 10 of 16
Table 6. Input Voltage Range and LSB Values
Binary Output
Analog Input Voltage Range
Defined as
±10 V
±5 V
±2.5 V
0 V to +10 V
0 V to +5 V
Code Designation
COB1
COB1
or CTC2
or CTC2
CSB3
One Least Significant Bit (LSB)
FSR
20 V
10 V
5 V
10 V
5 V
2n
n = 8
78.13 mV
39.06 mV
19.53 mV
39.06 mV
19.53 mV
n = 10
19.53 mV
9.77 mV
4.88 mV
9.77 mV
4.88 mV
n = 12
4.88 mV
2.44 mV
1.22 mV
2.44 mV
1.22 mV
Transition Values
MSB
LSB
000. . . 0004
+Full scale
10 V 3/2 LSB
5 V 3/2 LSB
2.5 V 3/2 LSB
10 V 3/2 LSB
5 V 3/2 LSB
011. . . 111
Midscale
0
5 V
2.5 V
111. . . 110
Full scale
10 V + 1/2 LSB
5 V + 1/2 LSB
2.5 V + 1/2 LSB
0 V + 1/2 LSB
1 COB = complementary offset binary.
2 CTC = complementary twos complement; obtained by using the complement of the most significant bit (MSB). MSB is available on Pin 8.
3 CSB = complementary straight binary.
4 Voltages given are the nominal value for transition to the code specified.
OFFSET ADJUSTMENT
The zero adjust circuit consists of a potentiometer connected
across ±VS with its slider connected through a 1.8 MΩ resistor
to COMPARATOR IN (Pin 11) for all ranges. As shown in
Figure 9, the tolerance of this fixed resistor is not critical, and a
carbon composition type is generally adequate. Using a carbon
composition resistor with a 1200 ppm/°C tempco contributes
a worst-case offset tempco of 8 × 244 × 106 × 1200 ppm/°C =
2.3 ppm/°C of FSR if the offset adjustment potentiometer is set
at either end of its adjustment range. Because the maximum
offset adjustment required is typically no more than ±4 LSB,
use of a carbon composition offset summing resistor typically
contributes no more than 1 ppm/°C of FSR offset tempco.
01
20
2-
0
09
ADADC80
1.8M
+15V
–15V
10k
TO
100k
11
COMPARATOR
IN
0
120
2-
010
Figure 9. Offset Adjustment Circuit
An alternative offset adjust circuit, which contributes negligible
offset tempco if metal film resistors (tempco < 100 ppm/°C) are
used, is shown in Figure 10. Note that the abbreviation MF in
Figure 10 and Figure 12 refer to metal film resistors.
ADADC80
180k
MF
180k
MF
22k
MF
+15V
–15V
10k
TO
100k
OFFSET
ADJUST
A
11
COMPARATOR
IN
0
120
2-
0
1
Figure 10. Low Tempco Zero Adjustment Circuit
In either zero adjust circuit, the fixed resistor connected to
COMPARATOR IN (Pin 11) should be located close to this pin
to keep the pin connection runs short. Pin 11 is quite sensitive
to external noise pickup.
GAIN ADJUSTMENT
The gain adjust circuit consists of a potentiometer connected
across ±VS with its slider connected through a 10 MΩ resistor
to the GAIN ADJUST (Pin 16), as shown in Figure 11.
ADADC80
10M
+15V
–15V
10k
TO
100k
GAIN
ADJUST
0.01F
16
GAIN
ADJUST
0
120
2-
0
12
Figure 11. Gain Adjustment Circuit
An alternative gain adjust circuit, which contributes negligible
gain tempco if metal film resistors (tempco < 100 ppm/°C) are
used, is shown in Figure 12.
ADADC80
270k
MF
270k
MF
+15V
–15V
10k
TO
100k
0.1F
6.8k
16
GAIN
ADJUST
Figure 12. Low Tempco Gain Adjustment Circuit
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