參數(shù)資料
型號(hào)： AD9992BBCZ
廠商： ANALOG DEVICES INC
元件分類： 消費(fèi)家電
英文描述： 12-Bit CCD Signal Processor with Precision Timing Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA105
封裝： 8 X 8 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-225, CSPBGA-105
文件頁(yè)數(shù)： 43/92頁(yè)
文件大?。?/td> 718K
代理商： AD9992BBCZ
AD9992
MODE Registers
The MODE registers are used to select the field timing of the
AD9992. Typically, all of the field, V-sequence, and V-pattern
information is programmed into the AD9992 at startup. During
operation, the MODE registers allow the user to select any com-
bination of field timing to meet the requirements of the system.
The advantage of using the MODE registers in conjunction with
preprogrammed timing is that it greatly reduces the system pro-
gramming requirements during camera operation. Only a few
register writes are required when the camera operating mode is
changed, rather than having to program all of the vertical timing
information with each camera mode change.
Rev. 0 | Page 43 of 92
A basic still camera application can require six fields of vertical
timing—one for draft mode operation, one for autofocusing,
and four for still image readout. All of the register timing
information for the six fields is loaded at startup. Then, during
camera operation, the MODE registers select which field timing is
active, depending on how the camera is being used.
Table 19 shows how the MODE registers are used. The MODE
register (Address 0x2A) specifies how many total fields are
used. Any value from 1 to 7 can be selected using these three
bits. The other two registers (0x2B and 0x2C) are used to select
Table 19. MODE Registers—VD Updated
Address
Name
Length
2A
MODE
3b
2B
FIELD0
5b
FIELD1
5b
FIELD2
5b
FIELD3
5b
FIELD4
5b
2C
FIELD5
5b
FIELD6
5b
which of the programmed fields are used and in which order.
Up to seven fields can be used in a single MODE write. The
AD9992 starts with the field timing specified by FIELD0, and
on the next VD, switches to the timing specified by FIELD1,
and so on. After completing the total number of fields specified
by MODE, the AD9992 repeats by starting at the first field. This
continues until a new write to the MODE register occurs. Figure
53 shows example MODE register settings for different field
configurations.
Note that only a write to Address 0x2C properly resets the field
counter. Therefore, when changing the values in any of the
mode registers, it is recommended that all three registers are
updated together in the same field (VD period).
Caution
The MODE registers are SCK updated by default. If they are
configured as VD-updated registers by writing Address 0xB4 =
0x03FF and Address 0xB5 = 0xFC00, the new MODE information
is updated on the second VD falling edge after the write occurs,
rather than on the first VD falling edge. See Figure 52 for an
example.
Description
Total number of fields to cycle through. Set from 1 to 7.
Selected FIELD (from FIELD registers in configurable memory) for the first field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the second field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the third field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the fourth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the fifth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the sixth field to cycle through.
Selected FIELD (from FIELD registers in configurable memory) for the seventh field to cycle through.
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