參數(shù)資料
型號(hào)： AD9985KSTZ-110
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 29/32頁(yè)
文件大?。?/td> 349K
代理商： AD9985KSTZ-110
AD9985
PCB LAYOUT RECOMMENDATIONS
The AD9985 is a high precision, high speed analog device. As
such, to get the maximum performance from the part, it is
important to have a well laid out board. The following is a guide
for designing a board using the AD9985.
Rev. 0 | Page 29 of 32
ANALOG INTERFACE INPUTS
Using the following layout techniques on the graphics inputs is
extremely important.
Minimize the trace length running into the graphics inputs.
This is accomplished by placing the AD9985 as close as possible
to the graphics VGA connector. Long input trace lengths are
undesirable because they pick up more noise from the board
and other external sources.
Place the 75 termination resistors (see Figure 3) as close to
the AD9985 chip as possible. Any additional trace length
between the termination resistors and the input of the AD9985
increases the magnitude of reflections, which will corrupt the
graphics signal.
Use 75 matched impedance traces. Trace impedances other
than 75 will also increase the chance of reflections.
The AD9985 has very high input bandwidth (500 MHz). While
this is desirable for acquiring a high resolution PC graphics
signal with fast edges, it means that it will also capture any high
frequency noise present. Therefore, it is important to reduce the
amount of noise that gets coupled to the inputs. Avoid running
any digital traces near the analog inputs.
Due to the high bandwidth of the AD9985, low-pass filtering
the analog inputs can sometimes help to reduce noise. (For
many applications, filtering is unnecessary.) Experiments have
shown that placing a series ferrite bead prior to the 75
termination resistor is helpful in filtering out excess noise.
Specifically, the part used was the #2508051217Z0 from Fair-
Rite, but each application may work best with a different bead
value. Alternately, placing a 100 to 120 resistor between the
75 termination resistor and the input coupling capacitor can
also be beneficial.
POWER SUPPLY BYPASSING
It is recommended to bypass each power supply pin with a
0.1 μF capacitor. The exception is when two or more supply pins
are adjacent to each other. For these groupings of powers/
grounds, it is necessary to have only one bypass capacitor. The
fundamental idea is to have a bypass capacitor within about
0.5 cm of each power pin. Also, avoid placing the capacitor on
the opposite side of the PC board from the AD9985, as that
interposes resistive vias in the path.
The bypass capacitors should be physically located between the
power plane and the power pin. Current should flow from the
power plane to the capacitor to the power pin. Do not make the
power connection between the capacitor and the power pin.
Placing a via underneath the capacitor pads, down to the power
plane, is generally the best approach.
It is particularly important to maintain low noise and good
stability of PV
D
(the clock generator supply). Abrupt changes in
PV
D
can result in similarly abrupt changes in sampling clock
phase and frequency. This can be avoided by careful attention to
regulation, filtering, and bypassing. It is highly desirable to
provide separate regulated supplies for each of the analog
circuitry groups (V
D
and PV
D
).
Some graphic controllers use substantially different levels of
power when active (during active picture time) and when idle
(during horizontal and vertical sync periods). This can result in
a measurable change in the voltage supplied to the analog
supply regulator, which can in turn produce changes in the
regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PV
D
, from a different,
cleaner power source (for example, from a 12 V supply).
It is also recommended to use a single ground plane for the
entire board. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane.
Using multiple ground planes can be detrimental because each
separate ground plane is smaller, and long ground loops can
result.
In some cases, using separate ground planes is unavoidable. For
those cases, it is recommended to at least place a single ground
plane under the AD9985. The location of the split should be at
the receiver of the digital outputs. For this case it is even more
important to place components wisely because the current
loops will be much longer (current takes the path of least
resistance). An example of a current loop is shown in Figure 15.
A
N
A
L
O
G
G
R
O
U
N
D
P
L
A
N
E
P
O
W
E
R
P
L
A
N
E
A
D
9
8
8
3
A
D
I
G
I
T
A
L
U
T
P
U
T
R
A
C
E
D
I
G
I
T
A
L
G
R
O
U
N
D
P
L
A
N
E
D
I
G
I
T
A
L
D
A
T
A
R
E
C
E
I
V
E
R
0
Figure 15. Current Loop
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