參數(shù)資料
型號(hào)： AD9985KSTZ-110
廠商： ANALOG DEVICES INC
元件分類： 其它接口
英文描述： 110 MSPS/140 MSPS Analog Interface for Flat Panel Displays
中文描述： SPECIALTY INTERFACE CIRCUIT, PQFP80
封裝： LEAD FREE, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 18/32頁(yè)
文件大小： 349K
代理商： AD9985KSTZ-110
AD9985
Rev. 0 | Page 18 of 32
Hex
Address
Write and
Read or
Read Only
Bits
Default
Value
*****0**
Register Name
Function
Bit 2 – Red Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Bit 1 – Green Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Bit 0 – Blue Clamp Select. Logic 0 selects clamp to ground. Logic 1
selects clamp to midscale (voltage at Pin 37).
Sync Separator Threshold. Sets how many internal 5 MHz clock periods
the sync separator will count to before toggling high or low. This
should be set to some number greater than the maximum Hsync or
equalization pulsewidth.
Pre-Coast. Sets the number of Hsync periods that Coast becomes
active prior to Vsync.
Post-Coast. Sets the number of Hsync periods that Coast stays active
following Vsync.
Bit 7 – Hsync detect. It is set to Logic 1 if Hsync is present on the
analog interface; otherwise it is set to Logic 0.
Bit 6 – AHS: Active Hsync. This bit indicates which analog Hsync is
being used. (Logic 0 = Hsync Input Pin, Logic 1 = Hsync from Sync-on-
Green.)
Bit 5 – Input Hsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 4 – Vsync Detect. It is set to Logic 1 if Vsync is present on the analog
interface; otherwise it is set to Logic 0.
Bit 3 – AVS: Active Vsync. This bit indicates which analog Vsync is
being used. (Logic 0 = Vsync Input Pin, Logic 1 = Vsync from Sync
Separator.)
Bit 2 – Output Vsync Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bit 1 – Sync-on-Green Detect. It is set to Logic 1 if sync is present on
the Green video input; otherwise it is set to 0.
Bit 0 – Input Coast Polarity Detect. (Logic 0 = Active Low, Logic 1 =
Active High.)
Bits [7:2] Reserved for future use. Must be written to 111111 for proper
operation.
Bit 1 – 4:2:2 Output Formatting Mode (Logic 0 = 4:2:2 mode, Logic 1=
4:4:4 mode)
Bit 0 – Must be set to 0 for proper operation.
Reserved for future use.
Reserved for future use.
Reserved for future use.
Target Code for Auto Offset Operation.
Target Code for Auto Offset Operation.
******0*
*******0
11H
R/W
7:0
00100000
Sync Separator
Threshold
12H
R/W
7:0
00000000
Pre-Coast
13H
R/W
7:0
00000000
Post-Coast
14H
RO
7:0
Sync Detect
15H
R/W
7:2
111111**
Reserved
1
******1*
Output Formats
16H
17H
18H
19H
1AH
R/W
RO
RO
R/W
R/W
0
*******1
00000100
00000100
Reserved
Test Register
Test Register
Test Register
Red Target Code
Green Target
Code
Blue Target
Code
Reserved
Auto Offset
Enable
Hold Auto Offset
Reserved
Update Mode
Test Register
7:0
7:0
7:0
7:0
7:0
1BH
R/W
7:0
00000100
Target Code for Auto Offset Operation.
1CH
1DH
R/W
R/W
7:0
7
00010001
0*******
Must be written to 11h for proper operation.
Enables the auto offset circuitry.
1EH
R/W
6
5:2
1:0
7:0
*0******
**1001**
******10
0000****
Holds the offset output of the auto offset at the current value.
Must be written to 9 for proper operation.
Changes the update rate of the auto offset.
Must be set to default value.
*The AD9985 updates the PLL divide ratio only when the LSBs are written to (Register 02H).
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