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參數(shù)資料
| 型號： | AD9984AKSTZ-140 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 其它接口 |
| 英文描述： | High Performance 10-Bit Display Interface |
| 中文描述： | SPECIALTY INTERFACE CIRCUIT, PQFP80 |
| 封裝： | ROHS COMPLIANT, MS-026BEC, LQFP-80 |
| 文件頁數(shù)： | 24/44頁 |
| 文件大?。?/td> | 490K |
| 代理商： | AD9984AKSTZ-140 |
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AD9984A
2-WIRE SERIAL REGISTER MAP
The AD9984A is initialized and controlled by a set of registers that determine the operating modes. An external controller is employed to
write and read the control registers through the 2-wire serial interface port.
Rev. 0 | Page 24 of 44
Table 14. Control Register Map
Hex
Address
Read Only
0x00
RO
0x01
R/W
Read/Write,
Bits
7:0
7:0
Default
Value
0010 0000
0110 1001
Register Name
Chip Revision
PLL Div MSBs
Description
An 8-bit register that represents the silicon revision level.
The 8 MSBs (Bits[11:4] of the PLL Divider. Larger values mean the PLL
operates at a faster rate. This register should be loaded first when a
change is needed. (This gives the PLL more time to lock).
1
The 4 LSBs (Bits[3:0]) of the PLL Divider. Links to the PLL Div MSB to
make a 12-bit register.
1
VCO Range Select. Chooses the VCO frequency range (see the Clock
Generation section).
Charge Pump Current. Varies the current that drives the low-pass filter
(see the Clock Generation section).
External Clock Enable.
ADC Clock Phase Adjust. Larger values mean more delay. (1 LSB = T/32).
The 7 MSBs of the Red Channel Gain Control. Controls ADC input range
(contrast) of each respective channel. Larger values give less contrast.
The 2 LSBs of the Red Channel Gain Control. Links with Register 0x05
to form the 9-bit red gain that controls the ADC input range (contrast)
of the red channel. A lower value corresponds to a higher gain.
1
The 7 MSBs of the Green Channel Gain Control. Controls ADC input
range (contrast) of each respective channel. Larger values give less
contrast.
The 2 LSBs of the Green Channel Gain Control. Links to Register 0x07
to form the 9-bit green gain that controls the ADC input range (contrast)
of the green channel. A lower value corresponds to a higher gain.
1
The 7 MSBs of the Blue Channel Gain Control. Controls ADC input range
(contrast) of each respective channel. Larger values give less contrast.
The 2 LSBs of the Blue Channel Gain Control. Links to Register 0x09
to form the 9-bit blue gain that controls the ADC input range (contrast)
of the blue channel. A lower value corresponds to a higher gain.
1
The 8 MSBs of the Red Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.
1
The 3 LSBs of the Red Channel Offset Control. Links to Register 0x0B
to form the 11-bit red offset that controls the dc offset (brightness)
of the red channel in auto-offset mode.
The 8 MSBs of the Green Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.
1
The 3 LSBs of the Green Channel Offset Control. Links to Register 0x0D
to form the 11-bit green offset that controls the dc offset (brightness)
of the green channel in auto-offset mode.
The 8 MSBs of the Blue Channel Offset Control. Controls dc offset
(brightness) of each respective channel. Larger values decrease
brightness.
1
The 3 LSBs of the Blue Channel Offset Control. Links to Register 0x0F
to form the 11-bit blue offset that controls the dc offset (brightness)
of the blue channel in auto-offset mode.
Sets the threshold of the sync separator’s digital comparator.
0x02
R/W
7:4
1101 ****
PLL Div LSBs
0x03
R/W
7:6
01** ****
VCO/CPMP
5:3
**00 1***
0x04
0x05
R/W
R/W
2
7:3
6:0
**** *0**
1000 0***
*100 0000
Phase Adjust
Red Gain MSBs
0x06
R/W
7:6
00** ****
Red Gain LSBs
0x07
R/W
6:0
*100 0000
Green Gain MSBs
0x08
R/W
7:6
00** ****
Green Gain LSBs
0x09
R/W
6:0
*100 0000
Blue Gain MSBs
0x0A
R/W
7:6
00** ****
Blue Gain LSBs
0x0B
R/W
7:0
0100 0000
Red Offset MSBs
0x0C
R/W
7:5
000* ****
Red Offset LSBs
0x0D
R/W
7:0
0100 0000
Green Offset MSBs
0x0E
R/W
7:5
000* ****
Green Offset LSBs
0x0F
R/W
7:0
0100 0000
Blue Offset MSBs
0x10
R/W
7:5
000* ****
Blue Offset LSBs
0x11
R/W
7:0
0010 0000
Sync Separator
Threshold
Hsync Control
0x12
R/W
7
0*** ****
Hsync Source Override.
0 = The chip determines the active Hsync source.
1 = The active Hsync source is set by Reg. 0x12, Bit 6.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9984AKSTZ-170 | 功能描述:IC DISPLAY 10BIT 170MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標準包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應用:移動電話，手機，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應商設備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
| AD9984APCBZ | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 10-Bit Display Interface |
| AD9984KSTZ-110 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9984KSTZ-140 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9984KSTZ-170 | 制造商:Analog Devices 功能描述: |
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