參數(shù)資料
型號(hào)： AD9983AKCPZ-140
廠商： Analog Devices, Inc.
英文描述： High Performance 8-Bit Display Interface
中文描述： 高性能8位顯示接口
文件頁(yè)數(shù)： 34/44頁(yè)
文件大小： 470K
代理商： AD9983AKCPZ-140
AD9983A
Preliminary Technical Data
0x19—Bits[7:0] Clamp Placement
An 8-bit register that sets the position of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally, at a position established by
the clamp placement register (Register 0x19) and for a duration
set by the clamp duration register (Register 0x1A). Clamping is
started a clamp placement count(Register 0x19) of pixel periods
after the trailing edge of Hsync. The clamp placement may be
programmed to any value between 1 and 255. A value of 0 is not
supported.
The clamp should be placed during a time that the input signal
presents a stable black-level reference, usually the back porch
period between Hsync and the image. When EXTCLMP = 1,
this register is ignored. Power-up default setting is 8.
0x1A—Bits[7:0] Clamp Duration
An 8-bit register that sets the duration of the internally
generated clamp. When EXTCLMP = 0 (Register 0x18, Bit 4), a
clamp signal is generated internally at a position established by
the clamp placement register (and for a duration set by the
clamp duration register). Clamping begins a clamp placement
count (Register 0x19) of pixel periods after the trailing edge of
Hsync. The clamp duration may be programmed to any value
between 1 and 255. A value of 0 is not supported.
For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can
produce brightness changes at the top of the screen, and a slow
recovery from large changes in the average picture level (APL),
or bright-ness. When EXTCLMP = 1, this register is ignored.
Power-up default setting is 20 DDR.
0x1B—Bit[7] Clamp Polarity Override
This bit is used to override the internal circuitry that
determines the polarity of the clamp signal. The power-up
default setting is 0.
Rev. PrA | Page 34 of 44
Table 37. Clamp Polarity Override Settings
Override Bit
Result
0
Clamp polarity determined by chip
1
Clamp polarity determined by user
Register 0x1B, Bit 6
0x1B—Bit[6] Clamp Input Polarity
This bit indicates the polarity of the clamp signal only if Bit 7 of
Register 0x1B = 1. The power-up default setting is 1.
Table 38. Clamp Polarity Override Settings
Value
Result
0
Active low external clamp
1
Active high external clamp
0x1B—Bit[5] Auto-Offset Enable
This bit selects between auto-offset mode and manual offset
mode (auto-offset disabled) (See the section on auto-offset
operation). The power-up default setting is 0.
Table 39. Auto-Offset Settings
Auto-Offset
0
1
0x1B—Bits[4:3] Auto-Offset Update Frequency
These bits control how often the auto-offset circuit is updated
(if enabled). Updating every 64 Hsyncs is recommended. The
power-up default setting is 11.
Result
Auto-offset is disabled
Auto-offset is enabled (manual offset mode)
Table 40. Auto-Offset Update Mode
Clamp Update
Result
00
Update offset every clamp period
01
Update offset every 16 clamp periods
10
Update offset every 64 clamp periods
11
Update offset every Vsync periods
0x1B—Bits[2:0]
Must be written to 011 for proper operation.
SOG CONTROL
0x1D—Bits[7:3] SOG Slicer Threshold
This register allows the comparator threshold of the SOG slicer
to be adjusted. This register adjusts it in steps of 8 mV, with the
minimum setting equaling 8 mV and the maximum setting
equaling 256 mV. The power-up default setting is 15 DDR and
corresponds to a threshold value of 128 mV.
0x1D—Bit[2] SOGOUT Polarity
This bit sets the polarity of the SOGOUT signal. The power-up
default setting is 0.
Table 41. SOGOUT Polarity Settings
SOGOUT
0
1
0x1D—Bits[1:0] SOGOUT Select
These register bits control what is output on the SOGOUT pin.
Options are the raw SOG from the slicer (this is the
unprocessed SOG signal produced from the sync slicer), the
raw Hsync, the regenerated sync from the sync filter, which can
generate missing syncs either due to coasting or drop-out, or
finally the filtered sync which excludes extraneous syncs not
occurring within the sync filter window. The power-up default
setting is 0.
Result
Active low
Active high
Table 42. SOGOUT Select
SOGOUT Select
00
01
10
11
Function
Raw SOG from sync slicer (SOGIN0 or SOGIN1)
Raw Hsync (HSYNC0 or HSYNC1)
Regenerated Hsync from sync filter
Filtered Hsync from sync filter
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9983AKCPZ-1401 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface
AD9983AKCPZ-170 功能描述:IC INTRFACE 8BIT 170MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9983AKCPZ-1701 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface
AD9983AKSTZ-140 功能描述:IC DISPLAY 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁(yè)面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1
AD9983AKSTZ-1401 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface
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