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參數(shù)資料
| 型號： | AD9983AKCPZ-1401 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 8-Bit Display Interface |
| 中文描述： | 高性能8位顯示接口 |
| 文件頁數(shù)： | 33/44頁 |
| 文件大?。?/td> | 470K |
| 代理商： | AD9983AKCPZ-1401 |
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Preliminary Technical Data
AD9983A
0x14—Bit[1] Vsync Duration Enable
This enables the Vsync duration block, which is designed to be
used with the Vsync filter. Setting the bit to 0 leaves the Vsync
output duration unchanged. Setting the bit to 1 sets the Vsync
output duration based on Register 0x15. Power-up duration is 0.
Rev. PrA | Page 33 of 44
Table 29. Vsync Duration Enable
Vsync Duration Bit
0
1
Result
Vsync output duration is unchanged
Vsync output duration is set by Register
0x15
0x15—Bits[7:0] Vsync Duration
This is used to set the output duration of the Vsync, and is
designed to be used with the Vsync filter. This is valid only if
Register 0x14, Bit 1 is set to 1. Power-up default is 10 DDR.
COAST AND CLAMP CONTROLS
0x16—Bits[7:0] Precoast
This register allows the internally generated coast signal to be
applied prior to the Vsync signal. This is necessary in cases
where pre-equalization pulses are present. The step size for this
control is one Hsync period. For precoast to work correctly, it is
necessary for the Vsync filter (0x14, Bit 2) and sync processing
filter (Register 0x20, Bit 1) both to be either enabled or disabled.
The power-up default is 00.
0x17—Bits[7:0] Postcoast
This register allows the internally generated Coast signal to be
applied following the Vsync signal. This is necessary in cases
where postequalization pulses are present. The step size for this
control is one Hsync period. For Postcoast to work correctly, it
is necessary for the Vsync filter (0x14, Bit 2) and sync
processing filter (0x20, Bit 1) both to be either enabled or
disabled. The power-up default is 00.
0x18—Bit[7] Coast Source
This bit is used to select the active Coast source. The choices are
the coast input pin or Vsync. If Vsync is selected, the additional
decision of using the Vsync input pin or the output from the
sync separator needs to be made (Register 0x14, Bits [7: 6]).
Table 30. Coast Source Selection Settings
Select
Result
0
Vsync (internal coast)
1
COAST input pin
0x18—Bit[6] Coast Polarity Override
This register is used to override the internal circuitry that
determines the polarity of the coast signal going into the PLL.
The power-up default setting is 0.
Table 31. Coast Polarity Override Settings
Override Bit
0
1
Result
Coast polarity determined by chip
Coast polarity determined by user
0x18—Bit[5] Coast Input Polarity
This register sets the input coast polarity when Bit 6 of
Register 0x18 = 1. The power-up default setting is 1.
Table 32. Coast Polarity Settings
Coast Polarity Bit
0
1
0x18—Bit[4] Clamp Source Select
This bit determines the source of clamp timing. A 0 enables the
clamp timing circuitry controlled by clamp placement and
clamp duration. The clamp position and duration is counted
from the leading edge of Hsync. A 1 enables the external clamp
input pin. The three channels are clamped when the clamp
signal is active. The polarity of clamp is determined by the
clamp polarity bit. The power-up default setting is 0.
Result
Coast polarity is negative
Coast polarity is positive
Table 33. Clamp Source Selection Settings
Clamp Source
0
1
0x18—Bit[3] Red Clamp Select
This bit determines whether the red channel is clamped to
ground or to midscale. The power-up default setting is 0.
Result
Internally generated clamp
Externally provided clamp signal
Table 34. Red Clamp Select Settings
Clamp
0
1
0x18—Bit[2] Green Clamp Select
This bit determines whether the green channel is clamped to
ground or to midscale. The power-up default setting is 0.
Result
Clamp to ground
Clamp to midscale
Table 35. Green Clamp Select Settings
Clamp
0
1
0x18—Bit[1] Blue Clamp Select
This bit determines whether the blue channel is clamped to
ground or to midscale. The power-up default setting is 0.
Result
Clamp to ground
Clamp to midscale
Table 36. Blue Clamp Select Settings
Clamp
0
1
Result
Clamp to ground
Clamp to midscale
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| AD9983AKCPZ-170 | High Performance 8-Bit Display Interface |
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD9983AKCPZ-170 | 功能描述:IC INTRFACE 8BIT 170MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9983AKCPZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKSTZ-140 | 功能描述:IC DISPLAY 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9983AKSTZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKSTZ-170 | 功能描述:IC DISPLAY 8BIT 170MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
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