- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373972 > AD9983AKCPZ-1401 (Analog Devices, Inc.) High Performance 8-Bit Display Interface PDF資料下載
參數(shù)資料
| 型號： | AD9983AKCPZ-1401 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High Performance 8-Bit Display Interface |
| 中文描述： | 高性能8位顯示接口 |
| 文件頁數(shù)： | 10/44頁 |
| 文件大小： | 470K |
| 代理商： | AD9983AKCPZ-1401 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁當(dāng)前第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
AD9983A
Preliminary Technical Data
Mnemonic
REFLO, REFHI
Rev. PrA | Page 10 of 44
Function
Input Amplifier Reference
Description
REFLO and REFHI are connected together through a 10 μF capacitor. These are used for
stability in the input ADC circuitry. See Figure 6.
For proper operation, the pixel clock generator PLL requires an external filter. Connect the
filter shown in Figure 7 to this pin. For optimal performance, minimize noise and parasitics
on this node. For more information, see the PCB Layout Recommendations section.
A reconstructed and phase-aligned version of the Hsync input. Both the polarity and
duration of this output can be programmed via serial bus registers. By maintaining
alignment with DATACK and Data, data timing with respect to Hsync can always be
determined.
Pin shared with A0, serial port address. This can be either a separated Vsync from a
composite signal or a direct pass through of the Vsync signal. The polarity of this output can
be controlled via a serial bus bit. The placement and duration in all modes can be set by the
graphics transmitter or the duration can be set by Register 0x14, Bit 1 and Register 0x15,
Bits[7:0]. This pin is shared with the A0 function, which does not affect Vsync Output
functionality. For more details on A0, see the description in the Serial Control Port section.
Pin shared with VSOUT. This pin selects the LSB of the serial port device address,
allowing two Analog Devices parts to be on the same serial bus. A high impedance
external pull-up resistor enables this pin to be read at power-up as 1, or a high
impedance, external pull-down resistor enables this pin to be read at power-up as a 0
and not interfere with the VSOUT functionality.
This pin outputs one of four possible signals (controlled by Register 0x1D, Bits[1:0]): raw
SOG, raw Hsync, regenerated Hsync from the filter, or the filtered Hsync. See Figure 9 to
view how this pin is connected. Other than slicing off SOG, the output from this pin
gets no additional processing on the AD9983A. Vsync separation is performed via the
sync separator.
This output will identify whether the current field (in an interlaced signal) is odd or even.
FILT
External Filter Connection
HSOUT
Horizontal Sync Output
VSOUT/A0
Vertical Sync Output
Serial Port Address Input 0
SOGOUT
Sync-On-Green Slicer
Output
O/E FIELD
Odd/Even Field Bit for
Interlaced Video
Serial Port Data I/O
Serial Port Data Clock
Data Output, Red Channel
Data Output, Green Channel
Data Output, Blue Channel
SDA
SCL
RED [7:0]
GREEN [7:0]
BLUE [7:0]
Data I/O for the I
2
C serial port.
Clock for the I
2
C serial port.
The main data outputs. Bit 9 is the MSB. The delay from pixel sampling time to output is
fixed. When the sampling time is changed by adjusting the phase register, the output
timing is shifted as well. The DATACK and HSOUT outputs are also moved, so the timing
relationship among the signals is maintained.
This is the main clock output signal used to strobe the output data and HSOUT into
external logic. Four possible output clocks can be selected with Register 0x20, Bits[7:6].
Three of these are related to the pixel clock (pixel clock, 90° phase-shifted pixel clock
and 2× frequency pixel clock). They are produced either by the internal PLL clock
generator or EXTCK and are synchronous with the pixel sampling clock. The fourth
option for the data clock output is an internally generated 12x pixel clock.
The sampling time of the internal pixel clock can be changed by adjusting the phase
register (Register 0x04). When this is changed, the pixel related DATACK timing is also
shifted. The data, DATACK, and HSOUT outputs are all moved so that the timing
relationship among the signals is maintained.
These pins supply power to the main elements of the circuit. They should be as quiet
and filtered as possible.
A large number of output pins (up to 29) switching at high speed (up to 170 MHz)
generates a lot of power supply transients (noise). These supply pins are identified
separately from the V
D
pins, so special care can be taken to minimize output noise
transferred into the sensitive analog circuitry. If the AD9983A is interfacing with lower
voltage logic, V
DD
can be connected to a lower supply voltage (as low as 1.8 V) for
compatibility.
The most sensitive portion of the AD9983A is the clock generation circuitry. These pins
provide power to the clock PLL and help the user design for optimal performance. The
designer should provide quiet, noise-free power to these pins.
This supplies power to the digital logic.
The ground return for all circuitry on-chip. It is recommended that the AD9983A be
assembled on a single solid ground plane, with careful attention to ground current paths.
DATACK
Data Clock Output
V
D
(1.8 V)
Main Power Supply
V
DD
(1.8 V to 3.3 V)
Digital Output Power Supply
PV
D
(1.8 V)
Clock Generator Power
Supply
DAV
DD
(1.8 V)
GND
Digital Input Power Supply
Ground
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9983AKCPZ-170 | High Performance 8-Bit Display Interface |
| AD9983AKCPZ-1701 | High Performance 8-Bit Display Interface |
| AD9984AKCPZ-140 | High Performance 10-Bit Display Interface |
| AD9984AKCPZ-170 | High Performance 10-Bit Display Interface |
| AD9984AKSTZ-140 | High Performance 10-Bit Display Interface |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9983AKCPZ-170 | 功能描述:IC INTRFACE 8BIT 170MSPS 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9983AKCPZ-1701 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKSTZ-140 | 功能描述:IC DISPLAY 8BIT 140MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD9983AKSTZ-1401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Performance 8-Bit Display Interface |
| AD9983AKSTZ-170 | 功能描述:IC DISPLAY 8BIT 170MSPS 80LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:- 特色產(chǎn)品:NXP - I2C Interface 標(biāo)準(zhǔn)包裝:1 系列:- 應(yīng)用:2 通道 I²C 多路復(fù)用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。