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參數(shù)資料
型號(hào)： AD9983A/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 22/44頁(yè)
文件大小： 0K
描述： KIT EVALUATION AD9983A
標(biāo)準(zhǔn)包裝： 1
系列： Advantiv®
主要目的： 視頻，視頻處理
嵌入式： 否
已用 IC / 零件： AD9983A
主要屬性： 3 x 8-Bit 140 MSPS ADC's
次要屬性： 集成式 PLL 和 VCO
已供物品： 板
AD9983A
Rev. 0 | Page 29 of 44
2-WIRE SERIAL CONTROL REGISTERS
CHIP IDENTIFICATION
0x00—Bits[7:0] Chip Revision
An 8-bit register that represents the silicon revision.
PLL DIVIDER CONTROL
0x01—Bits[7:0] PLL Divide Ratio MSBs
The 8 MSBs of the 12-bit PLL divide ratio PLLDIV.
The PLL derives a pixel clock from the incoming Hsync signal.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV
value determines the number of pixel times (pixels plus
horizontal blanking overhead) per line. This is typically 20% to
30% more than the number of active pixels in the display.
The 12-bit value of the PLL divider supports divide ratios from
2 to 4095 as long as the output frequency is within range. The
higher the value loaded in this register, the higher the resulting
clock frequency with respect to a fixed Hsync frequency.
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as a
function of horizontal and vertical display resolution and frame
rate (see Table 10). However, many computer systems do not
conform precisely to the recommendations and these numbers
should be used only as a guide. The display system manufacturer
should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV usually produces one or
more vertical noise bars on the display. The greater the error,
the greater the number of bars produced.
The power-up default value of PLLDIV is 1693. PLLDIVM =
0x69, PLLDIVL = 0xDX.
The AD9983A updates the full divide ratio only when the LSBs
are written. Writing to this register by itself does not trigger
an update.
0x02—Bits[7:4] PLL Divide Ratio LSBs
The 4 LSBs of the 12-bit PLL divide ratio PLLDIV.
The power-up default value of PLLDIV is 1693.
PLLDIVM = 0x69, PLLDIVL = 0xDX.
CLOCK GENERATOR CONTROL
0x03—Bits[7:6] VCO Range Select
Two bits that establish the operating range of the clock
generator. VCO range must be set to correspond to the desired
operating frequency (incoming pixel rate). The PLL gives the
best jitter performance at high frequencies. For this reason, in
order to output low pixel rates and still get good jitter performance,
the PLL actually operates at a higher frequency but then divides
down the clock rate afterwards. See Table 15 for the pixel rates
for each VCO range setting. The PLL output divisor is auto-
matically selected with the VCO range setting. The power-up
default value is 01.
Table 15. VCO Ranges
VCO Range
Results (Pixel Rates)
00
10 to 21
01
21 to 42
10
42 to 84
11
84 to 140
0x03—Bits[5:3] Charge Pump Current
Three bits that establish the current driving the loop filter in the
clock generator. The current must be set to correspond with the
desired operating frequency. The power-up default value is
current = 001.
Table 16. Charge Pump Currents
Ip2
Ip1
Ip0
Results (Current)
0
50
0
1
100
0
1
0
150
0
1
250
1
0
350
1
0
1
500
1
0
750
1
1500
0x03—Bit[2] External Clock Enable
This bit determines the source of the pixel clock.
Table 17. External Clock Select Settings
EXTCK
Function
0
Internally generated clock
1
Externally provided clock signal
A Logic 0 enables the internal PLL that generates the pixel clock
from an externally provided Hsync.
A Logic 1 enables the external EXTCK input pin. In this mode,
the PLL Divide Ratio (PLLDIV) is ignored. The clock phase
adjust (Phase) is still functional. The power-up default value is
EXTCK = 0.
PHASE ADJUST
0x04—Bits[7:3]
Phase adjustment for the DLL to generate the ADC clock. A 5-bit
value that adjusts the sampling phase in 32 steps across one
pixel time. Each step represents an 11.25° shift in sampling
phase. The power up default is 16.
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