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參數(shù)資料
| 型號(hào)： | AD9983A/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 20/44頁 |
| 文件大?。?/td> | 0K |
| 描述： | KIT EVALUATION AD9983A |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Advantiv® |
| 主要目的： | 視頻，視頻處理 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9983A |
| 主要屬性： | 3 x 8-Bit 140 MSPS ADC's |
| 次要屬性： | 集成式 PLL 和 VCO |
| 已供物品： | 板 |
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AD9983A
Rev. 0 | Page 27 of 44
Hex
Address
Read/Write,
Read Only
Bits
Default
Value
Register Name
Description
0x23
R/W
7:0
0000 1010
Sync Filter
Window Width
Sets the window of time around the regenerated Hsync leading
edge (in 25 ns steps) that sync pulses are allowed to pass through.
0x24
RO
7
_*** ****
Sync Detect
HSYNC0 Detection Bit.
0 = HSYNC0 is not active
1 = HSYNC0 is active
6
*_** ****
HSYNC1 Detection Bit.
0 = HSYNC1 is not active
1 = HSYNC1 is active
5
**_* ****
VSYNC0 Detection Bit.
0 = VSYNC0 is not active
1 = VSYNC0 is active
4
***_ ****
VSYNC1 Detection Bit.
0 = VSYNC1 is not active
1 = VSYNC1 is active
3
**** _***
SOGIN0 Detection Bit
0 = SOGIN0 is not active
1 = SOGIN0 is active
2
**** *_**
SOGIN1 Detection Bit
0 = SOGIN1 is not active
1 = SOGIN1 is active
1
**** **_*
COAST Detection Bit.
0 = External COAST is not active
1 = External COAST is active
0
**** ***_
CLAMP Detection Bit.
0 = External CLAMP is not active
1 = External CLAMP is active
0x25
RO
7
_*** ****
Sync Polarity
Detect
HSYNC0 Polarity.
0 = HSYNC0 polarity is active low
1 = HSYNC0 polarity is active high
6
*_** ****
HSYNC1 Polarity.
0 = HSYNC1 polarity is active low
1 = HSYNC1 polarity is active high
5
**_* ****
VSYNC0 Polarity.
0 = VSYNC0 polarity is active low
1 = VSYNC0 polarity is active high
4
***_ ****
VSYNC1 Polarity.
0 = VSYNC1 polarity is active low
1 = VSYNC1 polarity is active high
3
**** _***
COAST Polarity.
0 = External COAST polarity is active low
1 = External COAST polarity is active high
2
**** *_**
CLAMP Polarity.
0 = External CLAMP polarity is active low
1 = External CLAMP polarity is active high
1
**** **_*
Extraneous Pulses Detected.
0 = No extraneous pulses detected on HSYNCx
1 = Extraneous pulses detected on HSYNCx
0
Sync Filter Lock
0 = Sync filter unlocked
1 = Sync filter locked
0x26
RO
7:0
Hsyncs Per Vsync
MSBs
MSBs of Hsyncs per Vsync count.
0x27
RO
7:4
Hsyncs Per Vsync
LSBs
LSBs of Hsyncs per Vsync count.
0x28
R/W
7:0
1011 1111
TestReg1
Must be written to Reg. 0xBF for proper operation.
0x29
R/W
7:0
0000 0010
TestReg2
Must be written to Reg. 0x02 for proper operation.
0x2A
RO
7:0
TestReg3
Read-only bits for future use.
0x2B
RO
7:0
TestReg4
Read-only bits for future use.
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