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參數(shù)資料
| 型號(hào)： | AD9958BCPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 9/40頁 |
| 文件大?。?/td> | 1051K |
| 代理商： | AD9958BCPZ-REEL7 |
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AD9958
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Rev. 0 | Page 9 of 40
PIN 1
INDICATOR
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
SYNC_IN
SYNC_OUT
PWR_DWN_CTL
AVDD
AVDD
CH0_IOUT
CH0_IOUT
AGND
AVDD
AGND
CH1_IOUT
CH1_IOUT
10
11
12
13
14
35
34
AVDD
33
AVDD
32
NC
31
AVDD
30
AVDD
29
AVDD
36
AVDD
37
38
AVDD
39
40
AVDD
41
42
P1
1
A
1
A
1
D
1
A
2
A
2
A
2
R
2
R
2
C
2
A
2
A
2
L
2
N
1
A
4
4
4
4
4
5
5
5
5
5
4
4
TOP VIEW
(Not to Scale)
AD9958
5
5
NOTES
1. THE EXPOSED EPAD ON BOTTOM SIDE OF PACKAGE IS
AN ELECTRICAL CONNECTION AND MUST BE
SOLDERED TO GROUND.
2. PIN 49 IS DVDD_IO AND IS TIED TO 3.3V.
0
Figure 5. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
SYNC_IN
I/O
I
Description
Used to Synchronize Multiple AD9958s. Connects to the SYNC_OUT pin of the
master AD9958 device.
Used to Synchronize Multiple AD9958s. Connects to the SYNC_IN pin of the slave
AD9958 devices.
Active High Reset Pin. Asserting the MASTER_RESET pin forces the AD9958’s
internal registers to their default state, as described in the Register Map.
External Power-Down Control.
Analog Power Supply Pins (1.8 V).
2
SYNC_OUT
O
3
MASTER_RESET
I
4
5, 7, 11, 15, 19, 21,
26, 29, 30, 31, 33,
35, 36, 37, 39
6, 10, 12, 16, 18, 20,
25
45, 55
44, 56
8
9
13
14
17
PWR_DWN_CTL
AVDD
I
I
AGND
I
Analog Ground Pins.
DVDD
DGND
CH0_IOUT
CH0_IOUT
CH1_IOUT
CH1_IOUT
DAC_RSET
I
I
O
O
O
O
I
Digital Power Supply Pins (1.8 V).
Digital Power Ground Pins.
True DAC Output. Terminates into AVDD.
Complementary DAC Output. Terminates into AVDD.
True DAC Output. Terminates into AVDD.
Complementary DAC Output. Terminates into AVDD.
Establishes the Reference Current for all DACs. A 1.91 k resistor (nominal) is
connected from Pin 17 to AGND.
Complementary Reference Clock/Oscillator Input. When the REF_CLK is operated
in single-ended mode, this pin should be decoupled to AVDD or AGND with a
0.1 μF capacitor.
Reference Clock/Oscillator Input. When the REF_CLK is operated in single-ended
mode, this is the input. See Modes of Operation section for the reference clock
configuration.
22
REF_CLK
I
23
REF_CLK
I
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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