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參數(shù)資料
| 型號： | AD9958BCPZ-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 36/40頁 |
| 文件大小： | 1051K |
| 代理商： | AD9958BCPZ-REEL7 |
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AD9958
CONTROL REGISTER DESCRIPTIONS
CHANNEL SELECT REGISTER (CSR)
The CSR register determines if channels are enabled or disabled
by the status of the two channel enable bits. Both channels are
enabled by default. The CSR register also determines which
serial mode of operation is selected. In addition, the CSR
register offers a choice of MSB-first or LSB-first format. The
functionality of each bit is detailed as follows:
Rev. 0 | Page 36 of 40
The CSR is comprised of one byte located in Register 0x00.
CSR <0> LSB-first.
CSR <0> = 0 (default), the serial interface accepts serial data in
MSB-first format. CSR <0> = 1, the serial interface accepts
serial data in LSB-first format.
CSR <2:1> Serial I/O mode select.
CSR <2:1> 00 = Single bit serial (2-wire mode).
01 = Single bit serial (3-wire mode).
10 = 2-bit serial mode.
11 = 4-bit serial mode.
See the Serial I/O Modes of Operation section for more details.
CSR <3> = must be set to 0.
CSR <7:6> channel enable bits.
CSR <7:4> bits are active immediately after being written. They
do not require an I/O update to take effect.
There are two sets of channel registers and profile registers, one
per channel. This is not shown in the channel or profile register
map. The addresses of both channel registers and profile
registers are the same for each channel. Therefore, the channel
enable bits distinguish each channel’s channel registers and
profile registers values.
For example,
CSR <7:6> = 10, only Channel 1 receives commands from the
channel registers and profile registers.
CSR <7:6> = 01, only Channel 0 receives commands from the
channel registers and profile registers.
CSR <7:6> = 11, both Channel 0 and Channel 1 receive
commands from the channel registers and profile registers.
Function Register 1 (FR1) Description
FR1 is comprised of three bytes located in Register 0x01. The
FR1 is used to control the mode of operation of the chip. The
functionality of each bit is detailed as follows:
FR1 <0> manual software synchronization bit.
FR1 <0> = 0 (default), the software manual synchronization
feature of multiple devices is inactive. FR1 <0> = 1. The manual
software synchronization feature of multiple devices is active.
See the Synchronizing Multiple AD9958 Devices section for
details.
FR1 <1> manual hardware synchronization bit.
FR1<1> = 0 (default), the manual hardware synchronization
feature of multiple devices is inactive.FR1 <1> = 1, the manual
hardware synchronization feature of multiple devices is active.
FR1 <2:3>. See the Synchronizing Multiple AD9958 Devices
section for details.
FR1 <4> DACs reference power-down.
FR1 <4> = 0 (default). DACs reference is enabled. FR1 <4> = 1.
DAC reference is powered down.
FR1 <5> SYNC_CLK disable.
FR1 <5> = 0 (default), the SYNC_CLK pin is active.
FR1 <5> = 1. The SYNC_CLK pin assumes a static Logic 0
state (disabled). In this state, the pin drive logic is shut down.
However, the synchronization circuitry remains active
internally to maintain normal device operation.
FR1 <6> external power-down mode.
FR1 <6> = 0 (default). The external power-down mode is in the
fast recovery power-down mode. In this mode, when the
PWR_DWN_CTL input pin is high, the digital logic and the
DACs digital logic are powered down. The DACs bias circuitry,
PLL, oscillator, and clock input circuitry are not powered down.
FR1 <6> = 1. The external power down mode is in the full
power-down mode. In this mode, when the PWR_DWN_CTL
input pin is high, all functions are powered down. This includes
the DACs and PLL, which take a significant amount of time to
power up.
FR1 <7> clock input power-down.
FR1 <7> = 0 (default). The clock input circuitry is enabled for
operation. FR1 <7> = 1. The clock input circuitry is disabled
and is in a low power dissipation state.
FR1 <9:8> modulation level bits.
The modulation (FSK, PSK, and ASK) level bits control the level
(2/4/8/16) of modulation to be performed for a channel. See the
Modulation Mode section for more details.
FR1<10:11> RU/RD bit.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
| AD9959_08 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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