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參數(shù)資料
| 型號(hào)： | AD9957 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器與18位智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 52/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957 |
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AD9957
Bit
No.
11
Rev. 0 | Page 52 of 60
Mnemonic
PDCLK Enable
Description
0: the PDCLK pin is disabled and forced to a static Logic 0 state; the internal clock signal continues to operate
and provide timing to the data assembler.
1: the internal PDCLK signal appears at the PDCLK pin (default).
0: normal PDCLK polarity; Q-data associated with Logic 1, I-data with Logic 0 (default).
1: inverted PDCLK polarity.
0: normal TxEnable polarity; Logic 0 is standby, Logic 1 is transmit (default).
1: inverted TxEnable polarity; Logic 0 is transmit, Logic 1 is standby.
0: an I/Q data pair is delivered as I-data first followed by Q-data (default).
1: an I/Q data pair is delivered as Q-data first followed by I-data.
0: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output in
the order listed (default).
1: simultaneous application of amplitude, phase and frequency changes to the DDS arrive at the output
simultaneously.
Ineffective when CFR1 Bits<25:24> = 01b.
0: when the TxENABLE pin is false, the data assembler ignores the input data and internally forces zeros on
the baseband signal path (default).
1: when the TXENABLE pin is false, the data assembler ignores the input data and internally forces the last
value received on the baseband signal path.
0: enables the SYNC_SMP_ERR pin to indicate (active high) detection of a synchronization pulse
sampling error.
1: the SYNC_SMP_ERR pin is forced to a static Logic 0 condition (default).
10
PDCLK Invert
9
TxEnable Invert
8
Q First Data
Pairing
Matched Latency
Enable
7
6
Data Assembler
Hold Last Value
5
Sync Timing
Validation Disable
4:0
Not Available
Control Function Register 3 (CFR3)
Address 0x02, four bytes are assigned to this register.
Table 20. Bit Descriptions for CFR3 Register
Bit
No.
Mnemonic
31:30
DRV0
29:27
Not Available
26:24
VCO SEL
23:22
Not Available
21:19
I
CP
18:16
Not Available
15
REFCLK Input
Divider Bypass
14
REFCLK Input
Divider ResetB
13:9
Not Available
8
PLL Enable
Description
Controls REFCLK_OUT pin (see Table 7 for details); default is 00b.
Selects frequency band of the VCO in the REFCLK PLL (see Table 9 for details); default is 111b.
Selects the charge pump current in the REFCLK PLL (see Table 9 for details); default is 111b.
0: input divider is selected (default).
1: input divider is bypassed.
0: input divider is reset.
1: input divider operates normally (default).
0: REFCLK PLL bypassed (default).
1: REFCLK PLL enabled.
This 7-bit number is divide modulus of the REFCLK PLL feedback divider; default is 0000000b.
7:1
0
N
Not Available
Auxiliary DAC Control Register
Address 0x03, four bytes are assigned to this register.
Table 21. Bit Descriptions for Auxiliary DAC Control Register
Bit(s)
Mnemonic
Description
31:8
Not Available
7:0
FSC
This 8-bit number controls the full-scale output current of the main DAC (see the Auxiliary DAC section);
default is 0xFF.
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
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