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參數資料
| 型號： | AD9957 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數字上變頻器與18位智商數據路徑和14位DAC |
| 文件頁數： | 26/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957 |
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AD9957
RAM CONTROL
RAM OVERVIEW
The AD9957 has an integrated 1024 × 32-bit RAM. This RAM
is only accessible when the AD9957 is operating in QDUC or
interpolating DAC mode. The RAM has two fundamental
modes of operation: data entry/retrieve mode and playback
mode. The mode is selected by programming the RAM enable
bit in CFR1 via the serial I/O port.
Rev. 0 | Page 26 of 60
Data entry/retrieve mode is used to load or read back the RAM
contents via the serial I/O port. Playback mode is used to
deliver RAM data to one of two internal destinations: the
baseband scaling multipliers (see Figure 25, the IS and QS
labels) or the baseband signal chain (see Figure 25, the I and Q
labels). In both cases, the RAM can be used to apply an
arbitrary, time-varying waveform to the selected destination. A
block diagram of the RAM and its control elements is shown in
Figure 39.
The external parallel data port is disabled when the baseband
signal path serves as the RAM playback destination.
RAM
32
10
Q
STATE
MACHINE
SCLK
I/O_RESET
SDIO
CS
RT
END ADDRESS
START ADDRESS
10
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
RAM
SEGMENT
REGISTERS
S
A
D
U/D
32
2
(MSBs)
(LSBs)
16
0
Figure 39. RAM Block Diagram
In Figure 39, the serial I/O port is used to program the contents
of the two RAM segment registers as well as to load and retrieve
the RAM contents. The state machine takes care of incrementing
or decrementing the RAM address locations and controlling the
timing of the RAM address and data for proper operation. The
I-channel and Q-channel multiplexers route RAM data to
baseband scaling multipliers (IS/QS) or directly to the baseband
data pathway (I/Q) when the RAM is used in playback mode.
The state of the RAM playback destination bit determines the
destination of the RAM data during playback.
An I/O update (or a profile change) is necessary to enact a state
change of the RAM enable or RAM playback destination bits, or
any of the RAM segment register bits.
The 32-bit RAM data bus is partitioned so that the 16 MSBs are
designated as I-channel bits and the 16 LSBs are designated as
Q-channel bits. In playback mode, when driving data directly
into the baseband data path, the 16-bit data-words are consid-
ered to be signed (that is, twos complement) values. The 16-bit
I-and Q-words are MSB aligned with the 18-bit I and Q base-
band data path. The two remaining LSBs of each 18-bit baseband
channel are driven by the MSB of the respective channel. This
ensures correct polarity coding when the 16-bit I and Q data
from the RAM translates into 18-bit words for the baseband
data path. Alternatively, when the RAM is driving the baseband
scaling multipliers in playback mode, the RAM data is considered
to represent unsigned, fractional values with a range of 0 to 1 2
16
.
RAM SEGMENT REGISTERS
Two dedicated registers (RAM Segment Register 0 and RAM
Segment Register 1) control the operation of the RAM. Each
contains the following:
10-bit start address word
10-bit end address word
16-bit address step rate word
3-bit ram playback mode word
When programming these registers, the user must ensure that
the end address is greater than the start address.
With the RAM segment registers, the user can arbitrarily
partition the RAM into two independent memory segments.
The segment boundaries are specified with the start and end
address words in each RAM segment register. The playback
rate is controlled by the address step rate word (only meaningful
when the baseband scaling multipliers serve as the playback
destination). The playback mode of the RAM is controlled via
the RAM playback mode word.
RAM STATE MACHINE
The state machine acts as an address generator for the RAM. It
is clocked by either the serial I/O port (when the RAM is operating
in the load/retrieve mode) or the baseband data clock (when
the RAM is in playback mode). The state machine uses the
RAM mode bits of the active RAM segment register to establish
the proper sequence through the specified address range.
RAM TRIGGER (RT) PIN
The RAM state machine monitors the RT pin for logic state tran-
sitions. Any state transition triggers the state machine into action.
The direction of the logic state transition on the RT pin
determines which RAM segment register the state machine uses
for playback instructions. RAM Segment Register 0 is used if
the state machine detects a 0 to 1 transition; RAM Segment
Register 1 is used if a 1 to 0 transition is detected.
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| AD9957/PCBZ | 功能描述:BOARD EVAL AD9957 QUADRATURE MOD RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
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| AD9957BSVZ | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
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